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authorSteve Reinhardt <stever@eecs.umich.edu>2005-03-09 00:17:20 -0500
committerSteve Reinhardt <stever@eecs.umich.edu>2005-03-09 00:17:20 -0500
commitdbd60761f51d35d702332453658d5678ba005847 (patch)
treee073e03c4cb53d25e16a0d90d4a0292404d294b8 /sim
parentd191b14ff71f8b7af2098a29c2914d7332acd9be (diff)
parent4b69debac6ce72fe46a8d8b5284c740e338f06f6 (diff)
downloadgem5-dbd60761f51d35d702332453658d5678ba005847.tar.xz
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/m5-head --HG-- extra : convert_revision : daaeb6a596b08fbedd6a14833dcb3825c637d486
Diffstat (limited to 'sim')
-rw-r--r--sim/pyconfig/m5config.py8
1 files changed, 6 insertions, 2 deletions
diff --git a/sim/pyconfig/m5config.py b/sim/pyconfig/m5config.py
index f7bc90061..b5617c8ae 100644
--- a/sim/pyconfig/m5config.py
+++ b/sim/pyconfig/m5config.py
@@ -709,8 +709,12 @@ class Node(object):
if self.children:
# instantiate children in same order they were added for
# backward compatibility (else we can end up with cpu1
- # before cpu0).
- self.children.sort(lambda x,y: cmp(x.name, y.name))
+ # before cpu0). Changing ordering can also influence timing
+ # in the current memory system, as caches get added to a bus
+ # in different orders which affects their priority in the
+ # case of simulataneous requests. We should uncomment the
+ # following line once we take care of that issue.
+ # self.children.sort(lambda x,y: cmp(x.name, y.name))
children = [ c.name for c in self.children if not c.paramcontext]
print 'children =', ' '.join(children)