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authorSteve Reinhardt <stever@eecs.umich.edu>2006-10-08 10:53:24 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2006-10-08 10:53:24 -0700
commitd3fba5aa30adfb006b99895e869ed175213d0134 (patch)
tree461b216e3efae357acc2939fcc17d67bd5903e7c /src/arch/SConscript
parentbe36c808f77cfcb001aacb8cb32f45fb5909e00e (diff)
downloadgem5-d3fba5aa30adfb006b99895e869ed175213d0134.tar.xz
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU. Note that properly setting cpu_id on all CPUs is now required for correct operation. src/arch/SConscript: src/base/traceflags.py: src/cpu/base.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: src/python/m5/objects/BaseCPU.py: tests/configs/simple-atomic.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. --HG-- extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
Diffstat (limited to 'src/arch/SConscript')
-rw-r--r--src/arch/SConscript1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/SConscript b/src/arch/SConscript
index 59cea6211..dda1dea53 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -50,6 +50,7 @@ isa_switch_hdrs = Split('''
arguments.hh
faults.hh
isa_traits.hh
+ locked_mem.hh
process.hh
regfile.hh
stacktrace.hh