Merge ARM into the head. ARM will compile but may not actually work.

1 files changed, 6 insertions, 7 deletions

diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
index fec245b75..099327470 100644
--- a/src/arch/alpha/AlphaTLB.py
+++ b/src/arch/alpha/AlphaTLB.py
@@ -28,21 +28,20 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-class AlphaTLB(SimObject):
+
+from BaseTLB import BaseTLB
+
+class AlphaTLB(BaseTLB):
     type = 'AlphaTLB'
     abstract = True
     size = Param.Int("TLB size")
 
 class AlphaDTB(AlphaTLB):
     type = 'AlphaDTB'
-    cxx_namespace = 'AlphaISA'
-    cxx_class = 'DTB'
-
+    cxx_class = 'AlphaISA::DTB'
     size = 64
 
 class AlphaITB(AlphaTLB):
     type = 'AlphaITB'
-    cxx_namespace = 'AlphaISA'
-    cxx_class = 'ITB'
-
+    cxx_class = 'AlphaISA::ITB'
     size = 48