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authorGabe Black <gblack@eecs.umich.edu>2007-08-26 20:24:18 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-08-26 20:24:18 -0700
commit537239b278f7b8171d2eb09ef7f99c332266c48f (patch)
tree31984b63cc542f0a57ca96262477575ab0130c09 /src/arch/alpha/SConscript
parentf738afb865cd82487d6300259d6e87fb50660d2a (diff)
downloadgem5-537239b278f7b8171d2eb09ef7f99c332266c48f.tar.xz
Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
--HG-- extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
Diffstat (limited to 'src/arch/alpha/SConscript')
-rw-r--r--src/arch/alpha/SConscript11
1 files changed, 6 insertions, 5 deletions
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 4f293e22f..04bac3996 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -32,27 +32,28 @@
Import('*')
if env['TARGET_ISA'] == 'alpha':
+ Source('ev5.cc')
Source('faults.cc')
Source('floatregfile.cc')
Source('intregfile.cc')
+ Source('ipr.cc')
Source('miscregfile.cc')
+ Source('pagetable.cc')
Source('regfile.cc')
Source('remote_gdb.cc')
+ Source('tlb.cc')
Source('utility.cc')
+ SimObject('AlphaTLB.py')
+
if env['FULL_SYSTEM']:
SimObject('AlphaSystem.py')
- SimObject('AlphaTLB.py')
- Source('ev5.cc')
Source('idle_event.cc')
- Source('ipr.cc')
Source('kernel_stats.cc')
Source('osfpal.cc')
- Source('pagetable.cc')
Source('stacktrace.cc')
Source('system.cc')
- Source('tlb.cc')
Source('vtophys.cc')
Source('freebsd/system.cc')