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authorGabe Black <gblack@eecs.umich.edu>2007-03-07 20:04:45 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-03-07 20:04:45 +0000
commit8edc9d79cee3edd6d16a8254a0180aaa242974c7 (patch)
tree9ac7148f0862e81210fe929fcd61496ea7216727 /src/arch/alpha/ev5.cc
parentc82251326986affba0224460552236ebfe3447c2 (diff)
parent49527ab55312bf02dfce20c45db8f173b0c2324e (diff)
downloadgem5-8edc9d79cee3edd6d16a8254a0180aaa242974c7.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem --HG-- extra : convert_revision : d764fe37c71269a04fcede6cbf30e24262447e89
Diffstat (limited to 'src/arch/alpha/ev5.cc')
-rw-r--r--src/arch/alpha/ev5.cc28
1 files changed, 14 insertions, 14 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 8d13511ac..ec5090eb8 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -62,7 +62,7 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId)
AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
- tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect());
+ tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
tc->setNextPC(tc->readPC() + sizeof(MachInst));
delete reset;
@@ -76,12 +76,12 @@ void
AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
{
for (int i = 0; i < NumInternalProcRegs; ++i) {
- tc->setMiscReg(i, 0);
+ tc->setMiscRegNoEffect(i, 0);
}
- tc->setMiscReg(IPR_PAL_BASE, PalBase);
- tc->setMiscReg(IPR_MCSR, 0x6);
- tc->setMiscReg(IPR_PALtemp16, cpuId);
+ tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
+ tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
+ tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
}
@@ -94,13 +94,13 @@ AlphaISA::processInterrupts(CPU *cpu)
int ipl = 0;
int summary = 0;
- if (cpu->readMiscReg(IPR_ASTRR))
+ if (cpu->readMiscRegNoEffect(IPR_ASTRR))
panic("asynchronous traps not implemented\n");
- if (cpu->readMiscReg(IPR_SIRR)) {
+ if (cpu->readMiscRegNoEffect(IPR_SIRR)) {
for (int i = INTLEVEL_SOFTWARE_MIN;
i < INTLEVEL_SOFTWARE_MAX; i++) {
- if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+ if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
// See table 4-19 of the 21164 hardware reference
ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
summary |= (ULL(1) << i);
@@ -121,12 +121,12 @@ AlphaISA::processInterrupts(CPU *cpu)
}
}
- if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
- cpu->setMiscReg(IPR_ISR, summary);
- cpu->setMiscReg(IPR_INTID, ipl);
+ if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) {
+ cpu->setMiscRegNoEffect(IPR_ISR, summary);
+ cpu->setMiscRegNoEffect(IPR_INTID, ipl);
cpu->trap(new InterruptFault);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
- cpu->readMiscReg(IPR_IPLR), ipl, summary);
+ cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
}
}
@@ -148,7 +148,7 @@ SimpleThread::hwrei()
if (!(readPC() & 0x3))
return new UnimplementedOpcodeFault;
- setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
+ setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
if (!misspeculating()) {
if (kernelStats)
@@ -554,7 +554,7 @@ void
AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
{
for (int i = 0; i < NumInternalProcRegs; ++i) {
- dest->setMiscReg(i, src->readMiscReg(i));
+ dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
}
}