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authorGabe Black <gblack@eecs.umich.edu>2006-10-02 14:32:02 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-02 14:32:02 -0400
commite8ced44aead3b1a11ac7747b8d38ce5dba6c09d1 (patch)
tree2453c596489fbe786e6da2e21e0b5791bcbeaf88 /src/arch/alpha/ev5.cc
parente62b734b23d03c50fcd31d833f417207e4520d29 (diff)
parentf2acc3a4a303e4cc054eef62621499ebcbf8599b (diff)
downloadgem5-e8ced44aead3b1a11ac7747b8d38ce5dba6c09d1.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem src/cpu/ozone/cpu_impl.hh: Hand merged --HG-- extra : convert_revision : f8a5b0205bcb78c8f5e109f456fe7bca80a7abac
Diffstat (limited to 'src/arch/alpha/ev5.cc')
-rw-r--r--src/arch/alpha/ev5.cc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 796ed07de..7595423c3 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -554,6 +554,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
return NoFault;
}
+
void
AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
{
@@ -562,6 +563,7 @@ AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
}
}
+
/**
* Check for special simulator handling of specific PAL calls.
* If return value is false, actual PAL call will be suppressed.