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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-11-01 04:01:14 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-11-01 04:01:14 -0700 |
| commit | b6da5e2086b864149d65519333910d41351d4117 (patch) | |
| tree | cd0997ce638eb87661c3ff5456d27259fb9a11a7 /src/arch/alpha/ev5.cc | |
| parent | 1268e0df1f3d16d804b31005acf8067415771518 (diff) | |
| download | gem5-b6da5e2086b864149d65519333910d41351d4117.tar.xz | |
SE/FS: Get rid of uses of FULL_SYSTEM in Alpha.
Diffstat (limited to 'src/arch/alpha/ev5.cc')
| -rw-r--r-- | src/arch/alpha/ev5.cc | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 2bc913f92..06ba96003 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -44,8 +44,6 @@ namespace AlphaISA { -#if FULL_SYSTEM - //////////////////////////////////////////////////////////////////////// // // Machine dependent functions @@ -76,8 +74,6 @@ zeroRegisters(CPU *cpu) cpu->thread->setFloatReg(ZeroReg, 0.0); } -#endif - //////////////////////////////////////////////////////////////////////// // // @@ -201,10 +197,8 @@ ISA::readIpr(int idx, ThreadContext *tc) return retval; } -#ifdef DEBUG // Cause the simulator to break when changing to the following IPL int break_ipl = -1; -#endif void ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) @@ -264,10 +258,8 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) // write entire quad w/ no side-effect old = ipr[idx]; ipr[idx] = val; -#if FULL_SYSTEM if (tc->getKernelStats()) tc->getKernelStats()->context(old, val, tc); -#endif break; case IPR_DTB_PTE: @@ -294,14 +286,11 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) // only write least significant five bits - interrupt level ipr[idx] = val & 0x1f; -#if FULL_SYSTEM if (tc->getKernelStats()) tc->getKernelStats()->swpipl(ipr[idx]); -#endif break; case IPR_DTB_CM: -#if FULL_SYSTEM if (val & 0x18) { if (tc->getKernelStats()) tc->getKernelStats()->mode(Kernel::user, tc); @@ -309,7 +298,6 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) if (tc->getKernelStats()) tc->getKernelStats()->mode(Kernel::kernel, tc); } -#endif case IPR_ICM: // only write two mode bits - processor mode @@ -486,8 +474,6 @@ copyIprs(ThreadContext *src, ThreadContext *dest) } // namespace AlphaISA -#if FULL_SYSTEM - using namespace AlphaISA; Fault @@ -537,5 +523,3 @@ SimpleThread::simPalCheck(int palFunc) return true; } - -#endif // FULL_SYSTEM |