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| author | Nathan Binkert <nate@binkert.org> | 2008-09-27 21:03:48 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2008-09-27 21:03:48 -0700 |
| commit | cf7ddd8e8ac92cf5b90cd89a028414dd782c645a (patch) | |
| tree | fa29e1720ee26311b351d94bba7019ed8bbd7241 /src/arch/alpha/ev5.cc | |
| parent | 82f5723c7a8b245e1f60190a78b7fe383c2caf9b (diff) | |
| download | gem5-cf7ddd8e8ac92cf5b90cd89a028414dd782c645a.tar.xz | |
style: Make a style pass over the whole arch/alpha directory.
Diffstat (limited to 'src/arch/alpha/ev5.cc')
| -rw-r--r-- | src/arch/alpha/ev5.cc | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 166d42bc6..7dc02a611 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -459,8 +459,7 @@ MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) // really a control write ipr[idx] = val; - tc->getDTBPtr()->flushAddr(val, - DTB_ASN_ASN(ipr[IPR_DTB_ASN])); + tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN])); break; case IPR_DTB_TAG: { @@ -529,8 +528,7 @@ MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) // really a control write ipr[idx] = val; - tc->getITBPtr()->flushAddr(val, - ITB_ASN_ASN(ipr[IPR_ITB_ASN])); + tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN])); break; default: @@ -541,18 +539,17 @@ MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) // no error... } - void copyIprs(ThreadContext *src, ThreadContext *dest) { - for (int i = 0; i < NumInternalProcRegs; ++i) { + for (int i = 0; i < NumInternalProcRegs; ++i) dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); - } } } // namespace AlphaISA #if FULL_SYSTEM + using namespace AlphaISA; Fault |