diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2015-01-25 07:22:26 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2015-01-25 07:22:26 -0500 |
commit | f6742ea26e1a1cac21b486c7c5adad6fb6304e92 (patch) | |
tree | 416505359d690d558ba4f579123b5aba43da68d9 /src/arch/alpha/ev5.cc | |
parent | 0bd986015b2de741dc741f10e5afeaf5d8890ba1 (diff) | |
download | gem5-f6742ea26e1a1cac21b486c7c5adad6fb6304e92.tar.xz |
cpu: Remove all notion that we know when the cpu is misspeculating.
We have no way of knowing if a CPU model is on the wrong path with
our execute-in-execute CPU models. Don't pretend that we do.
Diffstat (limited to 'src/arch/alpha/ev5.cc')
-rw-r--r-- | src/arch/alpha/ev5.cc | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index d66ab42aa..d45786a83 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -161,8 +161,7 @@ ISA::readIpr(int idx, ThreadContext *tc) case IPR_DTB_PTE: { - TlbEntry &entry - = tc->getDTBPtr()->index(!tc->misspeculating()); + TlbEntry &entry = tc->getDTBPtr()->index(1); retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32; retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8; @@ -202,9 +201,6 @@ int break_ipl = -1; void ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) { - if (tc->misspeculating()) - return; - switch (idx) { case IPR_PALtemp0: case IPR_PALtemp1: @@ -484,10 +480,8 @@ SimpleThread::hwrei() CPA::cpa()->swAutoBegin(tc, pc.npc()); - if (!misspeculating()) { - if (kernelStats) - kernelStats->hwrei(); - } + if (kernelStats) + kernelStats->hwrei(); // FIXME: XXX check for interrupts? XXX return NoFault; |