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| author | Gabe Black <gabeblack@google.com> | 2020-01-09 02:46:30 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2020-01-22 07:05:44 +0000 |
| commit | 11f7344cdc215e6950e54f53956e4298ed1fee2b (patch) | |
| tree | 2597fb45e5e1f3ce0a07f42dfa0f1e35f9662cc5 /src/arch/alpha/ev5.cc | |
| parent | 0b7d8428af6b64ea48a41254990c2c54512a695b (diff) | |
| download | gem5-11f7344cdc215e6950e54f53956e4298ed1fee2b.tar.xz | |
arch: Get rid of the unused (and mostly undefined) zeroRegisters.
Change-Id: Iadf56e4e742506af7ae4b617d2dc5a56439aa407
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24188
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/alpha/ev5.cc')
| -rw-r--r-- | src/arch/alpha/ev5.cc | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 676d7a713..29910caa6 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -80,17 +80,6 @@ initCPU(ThreadContext *tc, int cpuId) delete reset; } -template <class CPU> -void -zeroRegisters(CPU *cpu) -{ - // Insure ISA semantics - // (no longer very clean due to the change in setIntReg() in the - // cpu model. Consider changing later.) - cpu->thread->setIntReg(ZeroReg, 0); - cpu->thread->setFloatReg(ZeroReg, 0); -} - //////////////////////////////////////////////////////////////////////// // // |