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author | Gabe Black <gabeblack@google.com> | 2020-01-29 16:49:40 -0800 |
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committer | Gabe Black <gabeblack@google.com> | 2020-02-01 12:31:56 +0000 |
commit | 4ae8d1c0ed18f351b52f421553b28fe109f87665 (patch) | |
tree | 08f688eed7d45f41f4c3af946bc0afdbf199aebf /src/arch/alpha/ev5.cc | |
parent | 6a7a5b30050d10a7d9cc9cd5614988871253298d (diff) | |
download | gem5-4ae8d1c0ed18f351b52f421553b28fe109f87665.tar.xz |
arch,sim: Merge initCPU into the ISA System classes.
Those classes are already ISA specific, so we can just move initCPU's
contents there and take it out of utility.hh, utility.cc, and the base
System's initState.
Change-Id: I28f0d0b50d83efe5116b0b24d20f8182a02823e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24905
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/alpha/ev5.cc')
-rw-r--r-- | src/arch/alpha/ev5.cc | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 4e2420dc9..3613d305c 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -63,26 +63,6 @@ getDTBPtr(T *tc) //////////////////////////////////////////////////////////////////////// // -// Machine dependent functions -// -void -initCPU(ThreadContext *tc, int cpuId) -{ - initIPRs(tc, cpuId); - - tc->setIntReg(16, cpuId); - tc->setIntReg(0, cpuId); - - Addr base = tc->readMiscRegNoEffect(IPR_PAL_BASE); - Addr offset = ResetFault().vect(); - - tc->pcState(base + offset); - - tc->activate(); -} - -//////////////////////////////////////////////////////////////////////// -// // // void |