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author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
commit | 537239b278f7b8171d2eb09ef7f99c332266c48f (patch) | |
tree | 31984b63cc542f0a57ca96262477575ab0130c09 /src/arch/alpha/faults.cc | |
parent | f738afb865cd82487d6300259d6e87fb50660d2a (diff) | |
download | gem5-537239b278f7b8171d2eb09ef7f99c332266c48f.tar.xz |
Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
Diffstat (limited to 'src/arch/alpha/faults.cc')
-rw-r--r-- | src/arch/alpha/faults.cc | 67 |
1 files changed, 60 insertions, 7 deletions
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc index 149729351..d81b55b33 100644 --- a/src/arch/alpha/faults.cc +++ b/src/arch/alpha/faults.cc @@ -29,13 +29,13 @@ * Kevin Lim */ +#include "arch/alpha/ev5.hh" #include "arch/alpha/faults.hh" +#include "arch/alpha/tlb.hh" #include "cpu/thread_context.hh" #include "cpu/base.hh" #include "base/trace.hh" -#if FULL_SYSTEM -#include "arch/alpha/ev5.hh" -#else +#if !FULL_SYSTEM #include "sim/process.hh" #include "mem/page_table.hh" #endif @@ -83,10 +83,6 @@ FaultName DtbAlignmentFault::_name = "unalign"; FaultVect DtbAlignmentFault::_vect = 0x0301; FaultStat DtbAlignmentFault::_count; -FaultName ItbMissFault::_name = "itbmiss"; -FaultVect ItbMissFault::_vect = 0x0181; -FaultStat ItbMissFault::_count; - FaultName ItbPageFault::_name = "itbmiss"; FaultVect ItbPageFault::_vect = 0x0181; FaultStat ItbPageFault::_count; @@ -176,6 +172,63 @@ void ItbFault::invoke(ThreadContext * tc) AlphaFault::invoke(tc); } +#else + +void ItbPageFault::invoke(ThreadContext * tc) +{ + Process *p = tc->getProcessPtr(); + Addr physaddr; + bool success = p->pTable->translate(pc, physaddr); + if(!success) { + panic("Tried to execute unmapped address %#x.\n", pc); + } else { + VAddr vaddr(pc); + VAddr paddr(physaddr); + + PTE pte; + pte.tag = vaddr.vpn(); + pte.ppn = paddr.vpn(); + pte.xre = 15; //This can be read in all modes. + pte.xwe = 1; //This can be written only in kernel mode. + pte.asn = p->M5_pid; //Address space number. + pte.asma = false; //Only match on this ASN. + pte.fonr = false; //Don't fault on read. + pte.fonw = false; //Don't fault on write. + pte.valid = true; //This entry is valid. + + tc->getITBPtr()->insert(vaddr.page(), pte); + } +} + +void NDtbMissFault::invoke(ThreadContext * tc) +{ + Process *p = tc->getProcessPtr(); + Addr physaddr; + bool success = p->pTable->translate(vaddr, physaddr); + if(!success) { + p->checkAndAllocNextPage(vaddr); + success = p->pTable->translate(vaddr, physaddr); + } + if(!success) { + panic("Tried to access unmapped address %#x.\n", (Addr)vaddr); + } else { + VAddr paddr(physaddr); + + PTE pte; + pte.tag = vaddr.vpn(); + pte.ppn = paddr.vpn(); + pte.xre = 15; //This can be read in all modes. + pte.xwe = 15; //This can be written in all modes. + pte.asn = p->M5_pid; //Address space number. + pte.asma = false; //Only match on this ASN. + pte.fonr = false; //Don't fault on read. + pte.fonw = false; //Don't fault on write. + pte.valid = true; //This entry is valid. + + tc->getDTBPtr()->insert(vaddr.page(), pte); + } +} + #endif } // namespace AlphaISA |