merge

1 files changed, 1 insertions, 1 deletions

diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index e93e16711..ff6de8d03 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -144,7 +144,7 @@ DtbFault::invoke(ThreadContext *tc)
     // read, like the EV5).  The EV6 approach is cleaner and seems to
     // work with EV5 PAL code, but not the other way around.
     if (!tc->misspeculating() &&
-        reqFlags.noneSet(Request::VPTE|Request::NO_FAULT)) {
+        reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
         // set VA register with faulting address
         tc->setMiscRegNoEffect(IPR_VA, vaddr);