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authorGabe Black <gblack@eecs.umich.edu>2010-09-13 19:26:03 -0700
committerGabe Black <gblack@eecs.umich.edu>2010-09-13 19:26:03 -0700
commit6833ca7eedd351596bb1518620af7465f5172fcd (patch)
tree4a67b3d591132dab3e8273fc9dfba606a1720e4a /src/arch/alpha/faults.cc
parent2edfcbbaee87c1a28351fc0dcd81d52d0d9102a4 (diff)
downloadgem5-6833ca7eedd351596bb1518620af7465f5172fcd.tar.xz
Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
Diffstat (limited to 'src/arch/alpha/faults.cc')
-rw-r--r--src/arch/alpha/faults.cc17
1 files changed, 9 insertions, 8 deletions
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 3264fc8b2..9d4eeda8a 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -110,7 +110,7 @@ FaultStat IntegerOverflowFault::_count;
#if FULL_SYSTEM
void
-AlphaFault::invoke(ThreadContext *tc)
+AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
FaultBase::invoke(tc);
countStat()++;
@@ -130,14 +130,14 @@ AlphaFault::invoke(ThreadContext *tc)
}
void
-ArithmeticFault::invoke(ThreadContext *tc)
+ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
FaultBase::invoke(tc);
panic("Arithmetic traps are unimplemented!");
}
void
-DtbFault::invoke(ThreadContext *tc)
+DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
// Set fault address and flags. Even though we're modeling an
// EV5, we use the EV6 technique of not latching fault registers
@@ -150,9 +150,10 @@ DtbFault::invoke(ThreadContext *tc)
tc->setMiscRegNoEffect(IPR_VA, vaddr);
// set MM_STAT register flags
+ MachInst machInst = inst->machInst;
tc->setMiscRegNoEffect(IPR_MM_STAT,
- (((Opcode(tc->getInst()) & 0x3f) << 11) |
- ((Ra(tc->getInst()) & 0x1f) << 6) |
+ (((Opcode(machInst) & 0x3f) << 11) |
+ ((Ra(machInst) & 0x1f) << 6) |
(flags & 0x3f)));
// set VA_FORM register with faulting formatted address
@@ -164,7 +165,7 @@ DtbFault::invoke(ThreadContext *tc)
}
void
-ItbFault::invoke(ThreadContext *tc)
+ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (!tc->misspeculating()) {
tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
@@ -178,7 +179,7 @@ ItbFault::invoke(ThreadContext *tc)
#else
void
-ItbPageFault::invoke(ThreadContext *tc)
+ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
Process *p = tc->getProcessPtr();
TlbEntry entry;
@@ -192,7 +193,7 @@ ItbPageFault::invoke(ThreadContext *tc)
}
void
-NDtbMissFault::invoke(ThreadContext *tc)
+NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
Process *p = tc->getProcessPtr();
TlbEntry entry;