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| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-05-05 03:22:31 -0400 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-05-05 03:22:31 -0400 |
| commit | 1da634ace00dbae3165228b36655a62538c7c88d (patch) | |
| tree | 3fbbc56c8ca5f2287caa16b8345990f4730e06ab /src/arch/alpha/faults.cc | |
| parent | 23b9792681d4cd794b0ad74138160a37b8bdac8f (diff) | |
| download | gem5-1da634ace00dbae3165228b36655a62538c7c88d.tar.xz | |
mem, alpha: Move Alpha-specific request flags
Move Alpha-specific memory request flags to an architecture-specific
header and map them to the architecture specific flag bit range.
Diffstat (limited to 'src/arch/alpha/faults.cc')
| -rw-r--r-- | src/arch/alpha/faults.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc index 2928f8d65..8bb781c13 100644 --- a/src/arch/alpha/faults.cc +++ b/src/arch/alpha/faults.cc @@ -147,7 +147,7 @@ DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) // on VPTE loads (instead of locking the registers until IPR_VA is // read, like the EV5). The EV6 approach is cleaner and seems to // work with EV5 PAL code, but not the other way around. - if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) { + if (reqFlags.noneSet(AlphaRequestFlags::VPTE | Request::PREFETCH)) { // set VA register with faulting address tc->setMiscRegNoEffect(IPR_VA, vaddr); |