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author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:13 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:13 -0400 |
commit | 1c8dfd92543aba5f49e464b17e7e8143fc01a58c (patch) | |
tree | 3c5b9059b07e8d0bccdf826249330bfcb8c5c1cc /src/arch/alpha/floatregfile.hh | |
parent | 63db33c4b1cd7a071c2a2fe47bda21a73618d054 (diff) | |
download | gem5-1c8dfd92543aba5f49e464b17e7e8143fc01a58c.tar.xz |
inorder-alpha-port: initial inorder support of ALPHA
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions
* * *
Remove namespace from header file. Causes compiler issues that are hard to find
* * *
Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time
* * *
Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)
Diffstat (limited to 'src/arch/alpha/floatregfile.hh')
-rw-r--r-- | src/arch/alpha/floatregfile.hh | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh index d5f9eec0f..a5a3a7861 100644 --- a/src/arch/alpha/floatregfile.hh +++ b/src/arch/alpha/floatregfile.hh @@ -42,6 +42,13 @@ class Checkpoint; namespace AlphaISA { +const int SingleWidth = 32; +const int SingleBytes = SingleWidth / 4; +const int DoubleWidth = 64; +const int DoubleBytes = DoubleWidth / 4; +const int QuadWidth = 128; +const int QuadBytes = QuadWidth / 4; + class FloatRegFile { public: @@ -54,6 +61,55 @@ class FloatRegFile void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); + + FloatReg + readReg(int floatReg) + { + return d[floatReg]; + } + + FloatReg + readReg(int floatReg, int width) + { + return readReg(floatReg); + } + + FloatRegBits + readRegBits(int floatReg) + { + return q[floatReg]; + } + + FloatRegBits + readRegBits(int floatReg, int width) + { + return readRegBits(floatReg); + } + + void + setReg(int floatReg, const FloatReg &val) + { + d[floatReg] = val; + } + + void + setReg(int floatReg, const FloatReg &val, int width) + { + setReg(floatReg, val); + } + + void + setRegBits(int floatReg, const FloatRegBits &val) + { + q[floatReg] = val; + } + + void + setRegBits(int floatReg, const FloatRegBits &val, int width) + { + setRegBits(floatReg, val); + } + }; } // namespace AlphaISA |