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authorNilay Vaish <nilay@cs.wisc.edu>2015-07-26 10:21:20 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-07-26 10:21:20 -0500
commit608641e23c7f2288810c3f23a1a63790b664f2ab (patch)
tree0656aaf9653e8d263f5daac0d5f0fe3190193ae5 /src/arch/alpha/idle_event.hh
parent6e354e82d9395b20f5f148cd545d0666b626e8ac (diff)
downloadgem5-608641e23c7f2288810c3f23a1a63790b664f2ab.tar.xz
cpu: implements vector registers
This adds a vector register type. The type is defined as a std::array of a fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now.
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