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authorAli Saidi <saidi@eecs.umich.edu>2007-03-07 15:04:44 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-03-07 15:04:44 -0500
commit49527ab55312bf02dfce20c45db8f173b0c2324e (patch)
treeb9212b195a7b253940aaaab5c8b9ef27e43d026e /src/arch/alpha/interrupts.hh
parentea7bdf9f60c404761dfc568d5291c75747a2dd88 (diff)
parent689cab36c90b56b3c8a7cda16d758acdd89f9de1 (diff)
downloadgem5-49527ab55312bf02dfce20c45db8f173b0c2324e.tar.xz
Merge zizzer:/bk/newmem
into zeep.pool:/tmp/newmem --HG-- extra : convert_revision : f078a05729b5fe464a06a58bc4adcb374f560572
Diffstat (limited to 'src/arch/alpha/interrupts.hh')
-rw-r--r--src/arch/alpha/interrupts.hh14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index 0500714ad..6453edf97 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -112,13 +112,13 @@ namespace AlphaISA
int ipl = 0;
int summary = 0;
- if (tc->readMiscReg(IPR_ASTRR))
+ if (tc->readMiscRegNoEffect(IPR_ASTRR))
panic("asynchronous traps not implemented\n");
- if (tc->readMiscReg(IPR_SIRR)) {
+ if (tc->readMiscRegNoEffect(IPR_SIRR)) {
for (int i = INTLEVEL_SOFTWARE_MIN;
i < INTLEVEL_SOFTWARE_MAX; i++) {
- if (tc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+ if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
// See table 4-19 of 21164 hardware reference
ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
summary |= (ULL(1) << i);
@@ -138,12 +138,12 @@ namespace AlphaISA
}
}
- if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) {
+ if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
newIpl = ipl;
newSummary = summary;
newInfoSet = true;
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
- tc->readMiscReg(IPR_IPLR), ipl, summary);
+ tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
return new InterruptFault;
} else {
@@ -154,8 +154,8 @@ namespace AlphaISA
void updateIntrInfo(ThreadContext *tc)
{
assert(newInfoSet);
- tc->setMiscReg(IPR_ISR, newSummary);
- tc->setMiscReg(IPR_INTID, newIpl);
+ tc->setMiscRegNoEffect(IPR_ISR, newSummary);
+ tc->setMiscRegNoEffect(IPR_INTID, newIpl);
newInfoSet = false;
}