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| author | Gabe Black <gabeblack@google.com> | 2018-10-18 17:34:08 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-22 21:15:45 +0000 |
| commit | 230b892fa3f484a46f4cd77f889f8793416b91e2 (patch) | |
| tree | 53b32ed7120d019399e36d04655487745bbba9ee /src/arch/alpha/isa.cc | |
| parent | 774770a6410abb129e2a19de1ca50d7c0c311fef (diff) | |
| download | gem5-230b892fa3f484a46f4cd77f889f8793416b91e2.tar.xz | |
arch: cpu: Stop passing around misc registers by reference.
These values are all basic integers (specifically uint64_t now), and
so passing them by const & is actually less efficient since there's a
extra level of indirection and an extra value, and the same sized value
(a 64 bit pointer vs. a 64 bit int) is being passed around.
Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
Reviewed-on: https://gem5-review.googlesource.com/c/13626
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/alpha/isa.cc')
| -rw-r--r-- | src/arch/alpha/isa.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc index 32d1aff65..685ddd479 100644 --- a/src/arch/alpha/isa.cc +++ b/src/arch/alpha/isa.cc @@ -114,7 +114,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) } void -ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) +ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid) { switch (misc_reg) { case MISCREG_FPCR: @@ -140,8 +140,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) } void -ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, - ThreadID tid) +ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid) { switch (misc_reg) { case MISCREG_FPCR: |