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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:22 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:22 -0700 |
commit | 3d39b6213265ceeb14b8089190e5a097f17fdc1b (patch) | |
tree | 60094f669d10e2c3f52aff53789819145663b095 /src/arch/alpha/isa.cc | |
parent | b398b8ff1ba7e181e010afd6219074cf6f683820 (diff) | |
download | gem5-3d39b6213265ceeb14b8089190e5a097f17fdc1b.tar.xz |
Alpha: Pull the MiscRegFile fully into the ISA object.
Diffstat (limited to 'src/arch/alpha/isa.cc')
-rw-r--r-- | src/arch/alpha/isa.cc | 111 |
1 files changed, 91 insertions, 20 deletions
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc index ed452cfc6..eee391a0d 100644 --- a/src/arch/alpha/isa.cc +++ b/src/arch/alpha/isa.cc @@ -29,51 +29,122 @@ */ #include "arch/alpha/isa.hh" +#include "base/misc.hh" #include "cpu/thread_context.hh" namespace AlphaISA { void -ISA::clear() +ISA::serialize(std::ostream &os) { - miscRegFile.clear(); + SERIALIZE_SCALAR(fpcr); + SERIALIZE_SCALAR(uniq); + SERIALIZE_SCALAR(lock_flag); + SERIALIZE_SCALAR(lock_addr); + SERIALIZE_ARRAY(ipr, NumInternalProcRegs); } -MiscReg -ISA::readMiscRegNoEffect(int miscReg) +void +ISA::unserialize(Checkpoint *cp, const std::string §ion) { - return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg); + UNSERIALIZE_SCALAR(fpcr); + UNSERIALIZE_SCALAR(uniq); + UNSERIALIZE_SCALAR(lock_flag); + UNSERIALIZE_SCALAR(lock_addr); + UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs); } -MiscReg -ISA::readMiscReg(int miscReg, ThreadContext *tc) -{ - return miscRegFile.readReg((MiscRegIndex)miscReg, tc); -} -void -ISA::setMiscRegNoEffect(int miscReg, const MiscReg val) +MiscReg +ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) { - miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val); + switch (misc_reg) { + case MISCREG_FPCR: + return fpcr; + case MISCREG_UNIQ: + return uniq; + case MISCREG_LOCKFLAG: + return lock_flag; + case MISCREG_LOCKADDR: + return lock_addr; + case MISCREG_INTR: + return intr_flag; + default: + assert(misc_reg < NumInternalProcRegs); + return ipr[misc_reg]; + } } -void -ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc) +MiscReg +ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) { - miscRegFile.setReg((MiscRegIndex)miscReg, val, tc); + switch (misc_reg) { + case MISCREG_FPCR: + return fpcr; + case MISCREG_UNIQ: + return uniq; + case MISCREG_LOCKFLAG: + return lock_flag; + case MISCREG_LOCKADDR: + return lock_addr; + case MISCREG_INTR: + return intr_flag; + default: + return readIpr(misc_reg, tc); + } } void -ISA::serialize(std::ostream &os) +ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) { - miscRegFile.serialize(os); + switch (misc_reg) { + case MISCREG_FPCR: + fpcr = val; + return; + case MISCREG_UNIQ: + uniq = val; + return; + case MISCREG_LOCKFLAG: + lock_flag = val; + return; + case MISCREG_LOCKADDR: + lock_addr = val; + return; + case MISCREG_INTR: + intr_flag = val; + return; + default: + assert(misc_reg < NumInternalProcRegs); + ipr[misc_reg] = val; + return; + } } void -ISA::unserialize(Checkpoint *cp, const std::string §ion) +ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, + ThreadID tid) { - miscRegFile.unserialize(cp, section); + switch (misc_reg) { + case MISCREG_FPCR: + fpcr = val; + return; + case MISCREG_UNIQ: + uniq = val; + return; + case MISCREG_LOCKFLAG: + lock_flag = val; + return; + case MISCREG_LOCKADDR: + lock_addr = val; + return; + case MISCREG_INTR: + intr_flag = val; + return; + default: + setIpr(misc_reg, val, tc); + return; + } } } |