Merge zizzer.eecs.umich.edu:/bk/newmem

into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

src/cpu/ozone/cpu_impl.hh:
    Hand merged

--HG--
extra : convert_revision : f8a5b0205bcb78c8f5e109f456fe7bca80a7abac

1 files changed, 5 insertions, 2 deletions

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 30959c72e..4fc9da3f3 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -779,10 +779,10 @@ decode OPCODE default Unknown::unknown() {
             }}, IsNonSpeculative, IsQuiesce);
             0x03: quiesceCycles({{
                 AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
-            }}, IsNonSpeculative, IsQuiesce);
+            }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
             0x04: quiesceTime({{
                 R0 = AlphaPseudo::quiesceTime(xc->tcBase());
-            }}, IsNonSpeculative);
+            }}, IsNonSpeculative, IsUnverifiable);
             0x10: ivlb({{
                 AlphaPseudo::ivlb(xc->tcBase());
             }}, No_OpClass, IsNonSpeculative);
@@ -795,6 +795,9 @@ decode OPCODE default Unknown::unknown() {
             0x21: m5exit({{
                 AlphaPseudo::m5exit(xc->tcBase(), R16);
             }}, No_OpClass, IsNonSpeculative);
+            0x31: loadsymbol({{
+                AlphaPseudo::loadsymbol(xc->tcBase());
+            }}, No_OpClass, IsNonSpeculative);
             0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
             0x40: resetstats({{
                 AlphaPseudo::resetstats(xc->tcBase(), R16, R17);