diff options
author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-02-12 09:26:47 -0800 |
---|---|---|
committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-02-12 09:26:47 -0800 |
commit | f78bc80bd75f6f4ebf080620b3aaeaee3b3e46cc (patch) | |
tree | 56134929157da94c31188651787a254e5b7b251b /src/arch/alpha/isa/decoder.isa | |
parent | 6b37bb67101803f12b6ed2bef714af583d03f814 (diff) | |
download | gem5-f78bc80bd75f6f4ebf080620b3aaeaee3b3e46cc.tar.xz |
Move store conditional result checking from SimpleAtomicCpu write
function into Alpha ISA description. write now just generically
returns a result value if the res pointer is non-null (which means
we can only provide a res pointer if we expect a valid result
value).
--HG--
extra : convert_revision : fb1c315515787f5fbbf7d1af7e428bdbfe8148b8
Diffstat (limited to 'src/arch/alpha/isa/decoder.isa')
-rw-r--r-- | src/arch/alpha/isa/decoder.isa | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 6df47ef7a..1da6a60f1 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -84,6 +84,9 @@ decode OPCODE default Unknown::unknown() { uint64_t tmp = write_result; // see stq_c Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; + if (tmp == 1) { + xc->setStCondFailures(0); + } }}, mem_flags = LOCKED, inst_flags = IsStoreConditional); 0x2f: stq_c({{ Mem.uq = Ra; }}, {{ @@ -96,6 +99,12 @@ decode OPCODE default Unknown::unknown() { // mailbox access, and we don't update the // result register at all. Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; + if (tmp == 1) { + // clear failure counter... this is + // non-architectural and for debugging + // only. + xc->setStCondFailures(0); + } }}, mem_flags = LOCKED, inst_flags = IsStoreConditional); } |