diff options
| author | Gabe Black <gabeblack@google.com> | 2017-11-02 01:58:38 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-11-02 09:43:35 +0000 |
| commit | 8be75f49fd37712e7cf04c0853bb7504f69a04d6 (patch) | |
| tree | f791cd8adccee52d054f5a10b62948021a3d121b /src/arch/alpha/isa/fp.isa | |
| parent | 97c68e8fc56baa39ce7901ac1f73d2ff79b550f2 (diff) | |
| download | gem5-8be75f49fd37712e7cf04c0853bb7504f69a04d6.tar.xz | |
alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.
The ISA parser used to generate different copies of exec functions
for each exec context class a particular CPU wanted to use. That's
since been changed so that those functions take a pointer to the base
ExecContext, so the code which would generate those extra functions
can be removed, and some functions which used to be templated on an
ExecContext subclass can be untemplated, or minimally less templated.
Now that some functions aren't going to be instantiated multiple times
with different signatures, there are also opportunities to collapse
templates and make many instruction definitions simpler within the
parser. Since those changes will be less mechanical, they're left for
later changes and will probably be done in smaller increments.
Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea
Reviewed-on: https://gem5-review.googlesource.com/5381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/alpha/isa/fp.isa')
| -rw-r--r-- | src/arch/alpha/isa/fp.isa | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa index ea692aeef..36bfde2dd 100644 --- a/src/arch/alpha/isa/fp.isa +++ b/src/arch/alpha/isa/fp.isa @@ -42,7 +42,7 @@ output exec {{ /// instruction in full-system mode. /// @retval Full-system mode: NoFault if FP is enabled, FenFault /// if not. Non-full-system mode: always returns NoFault. - inline Fault checkFpEnableFault(CPU_EXEC_CONTEXT *xc) + inline Fault checkFpEnableFault(ExecContext *xc) { Fault fault = NoFault; // dummy... this ipr access should not fault if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) { @@ -50,7 +50,7 @@ output exec {{ } return fault; } - inline Fault checkVectorEnableFault(CPU_EXEC_CONTEXT *xc) { + inline Fault checkVectorEnableFault(ExecContext *xc) { return std::make_shared<VectorEnableFault>(); } }}; @@ -206,7 +206,7 @@ output decoder {{ // FP instruction class execute method template. Handles non-standard // rounding modes. def template FloatingPointExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { if (trappingMode != Imprecise && !warnedOnTrapping) { @@ -250,7 +250,7 @@ def template FloatingPointExecute {{ // rounding mode control is needed. Like BasicExecute, but includes // check & warning for non-standard trapping mode. def template FPFixedRoundingExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { if (trappingMode != Imprecise && !warnedOnTrapping) { |