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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-17 19:27:50 -0800 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-17 19:27:50 -0800 |
| commit | 968048f56a5f866b267ad9961cbe8d16788bcc89 (patch) | |
| tree | 1ee95adb6f849be712772796899ee8d316b6ff76 /src/arch/alpha/isa/int.isa | |
| parent | c299c2562b68d75eb457c7206d3ec43e4cabcf14 (diff) | |
| download | gem5-968048f56a5f866b267ad9961cbe8d16788bcc89.tar.xz | |
Convert Alpha (and finish converting MIPS) to new
InstObjParam interface.
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/fp.isa:
src/arch/alpha/isa/int.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/isa/mem.isa:
src/arch/alpha/isa/pal.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/util.isa:
Get rid of CodeBlock calls to adapt to new InstObjParam interface.
src/arch/isa_parser.py:
Check template code for operands (in addition to snippets).
src/cpu/o3/alpha/dyn_inst.hh:
Add (read|write)MiscRegOperand calls to Alpha DynInst.
--HG--
extra : convert_revision : 332caf1bee19b014cb62c1ed9e793e793334c8ee
Diffstat (limited to 'src/arch/alpha/isa/int.isa')
| -rw-r--r-- | src/arch/alpha/isa/int.isa | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/arch/alpha/isa/int.isa b/src/arch/alpha/isa/int.isa index 45e096ebd..bd9c3ccd9 100644 --- a/src/arch/alpha/isa/int.isa +++ b/src/arch/alpha/isa/int.isa @@ -113,16 +113,14 @@ def format IntegerOperate(code, *opt_flags) {{ imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code) # generate declaration for register version - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags) + iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) exec_output = BasicExecute.subst(iop) if uses_imm: # append declaration for imm version - imm_cblk = CodeBlock(imm_code) - imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk, + imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_code, opt_flags) header_output += BasicDeclare.subst(imm_iop) decoder_output += BasicConstructor.subst(imm_iop) |