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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-12-08 10:55:33 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-12-08 10:55:33 -0800 |
| commit | 5a895ab92ce072c2b416267f171d67360dc63e4d (patch) | |
| tree | c974bf85285d34928787b2968a00a46811230467 /src/arch/alpha/isa/main.isa | |
| parent | f26051eb1a5b8f3522acbb871133de66278fd517 (diff) | |
| download | gem5-5a895ab92ce072c2b416267f171d67360dc63e4d.tar.xz | |
Alpha: Take advantage of new PCState syntax.
Diffstat (limited to 'src/arch/alpha/isa/main.isa')
| -rw-r--r-- | src/arch/alpha/isa/main.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index ffc267cd2..fa0086fc7 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -186,7 +186,8 @@ def operands {{ 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), - 'PCS': ('PCState', 'uq', None, ( None, None, 'IsControl' ), 4), + 'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4), + 'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4), 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1), 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1), 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1), |