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authorKorey Sewell <ksewell@umich.edu>2006-07-23 13:41:53 -0400
committerKorey Sewell <ksewell@umich.edu>2006-07-23 13:41:53 -0400
commit6e969c31c7c0671ce201f40dd67afad2e9fee832 (patch)
tree1a7a5bc1e52dd54ff3319837fa87c018d8dd08b0 /src/arch/alpha/isa/mem.isa
parentf9729e999f71895f6b53f8189bdff535e7c7b70e (diff)
parent19ca97af79f3a40111991b4f8375592c7ede65fa (diff)
downloadgem5-6e969c31c7c0671ce201f40dd67afad2e9fee832.tar.xz
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 --HG-- extra : convert_revision : be1e5dcb1c5025db8526e628c2060b1790d38227
Diffstat (limited to 'src/arch/alpha/isa/mem.isa')
-rw-r--r--src/arch/alpha/isa/mem.isa1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index 08a0a2343..a5dda7fc6 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -668,7 +668,6 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ completeAccTemplate.subst(completeacc_iop))
}};
-
def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \