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authorKorey Sewell <ksewell@umich.edu>2009-05-12 15:01:14 -0400
committerKorey Sewell <ksewell@umich.edu>2009-05-12 15:01:14 -0400
commit2012202b06a620998709f605f8f8692ad718294d (patch)
tree43a4817c6889723d480e7c66c0b22cfe022cb0ea /src/arch/alpha/isa/pal.isa
parentb569f8f0ed8dcf32347f0d4f68d2d7572a5d1353 (diff)
downloadgem5-2012202b06a620998709f605f8f8692ad718294d.tar.xz
inorder/alpha-isa: create eaComp object visible to StaticInst through ISA
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * *
Diffstat (limited to 'src/arch/alpha/isa/pal.isa')
-rw-r--r--src/arch/alpha/isa/pal.isa11
1 files changed, 3 insertions, 8 deletions
diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa
index 0931c1aec..c6c0fa95c 100644
--- a/src/arch/alpha/isa/pal.isa
+++ b/src/arch/alpha/isa/pal.isa
@@ -155,9 +155,7 @@ output header {{
int16_t disp;
/// Constructor
- HwLoadStore(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- StaticInstPtr _eaCompPtr = nullStaticInstPtr,
- StaticInstPtr _memAccPtr = nullStaticInstPtr);
+ HwLoadStore(const char *mnem, ExtMachInst _machInst, OpClass __opClass);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -168,11 +166,8 @@ output header {{
output decoder {{
inline
HwLoadStore::HwLoadStore(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass,
- StaticInstPtr _eaCompPtr,
- StaticInstPtr _memAccPtr)
- : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
- disp(HW_LDST_DISP)
+ OpClass __opClass)
+ : Memory(mnem, _machInst, __opClass), disp(HW_LDST_DISP)
{
memAccessFlags.clear();
if (HW_LDST_PHYS) memAccessFlags.set(Request::PHYSICAL);