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| author | Nathan Binkert <binkertn@umich.edu> | 2006-10-20 00:10:12 -0700 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2006-10-20 00:10:12 -0700 |
| commit | a4c6f0d69eda5d23b12576080d532ddf768fbdbe (patch) | |
| tree | 72863fc8729c977d15d1c60aeb8243407e964550 /src/arch/alpha/isa | |
| parent | 7245d4530d0c8367fa7b1adadcb55e1e8bd466e7 (diff) | |
| download | gem5-a4c6f0d69eda5d23b12576080d532ddf768fbdbe.tar.xz | |
Use PacketPtr everywhere
--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
Diffstat (limited to 'src/arch/alpha/isa')
| -rw-r--r-- | src/arch/alpha/isa/main.isa | 8 | ||||
| -rw-r--r-- | src/arch/alpha/isa/mem.isa | 10 |
2 files changed, 10 insertions, 8 deletions
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 0eb611a60..2024b1117 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -45,20 +45,22 @@ output header {{ #include <iostream> #include <iomanip> +#include "arch/alpha/faults.hh" #include "config/ss_compatible_fp.hh" #include "cpu/static_inst.hh" -#include "arch/alpha/faults.hh" #include "mem/request.hh" // some constructors use MemReq flags +#include "mem/packet.hh" }}; output decoder {{ +#include <cmath> + #include "base/cprintf.hh" #include "base/fenv.hh" #include "base/loader/symtab.hh" #include "config/ss_compatible_fp.hh" #include "cpu/thread_context.hh" // for Jump::branchTarget() - -#include <math.h> +#include "mem/packet.hh" using namespace AlphaISA; }}; diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa index fe69c36a5..02291ed6b 100644 --- a/src/arch/alpha/isa/mem.isa +++ b/src/arch/alpha/isa/mem.isa @@ -186,7 +186,7 @@ def template InitiateAccDeclare {{ def template CompleteAccDeclare {{ - Fault completeAcc(Packet *, %(CPU_exec_context)s *, + Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; }}; @@ -313,7 +313,7 @@ def template LoadInitiateAcc {{ def template LoadCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, + Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -437,7 +437,7 @@ def template StoreInitiateAcc {{ def template StoreCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, + Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -460,7 +460,7 @@ def template StoreCompleteAcc {{ def template StoreCondCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, + Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -535,7 +535,7 @@ def template MiscInitiateAcc {{ def template MiscCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, + Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { |