diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-31 16:02:28 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-31 16:02:28 -0500 |
| commit | ece796ab8af23705f3f4d7bd12ee623f3961c99e (patch) | |
| tree | 29f7e1786617c0eb5f57a59359c8cdb1d69743ba /src/arch/alpha/isa | |
| parent | 3c19c5f0f239b8d31a3a8acd03eff9923f19b6ee (diff) | |
| download | gem5-ece796ab8af23705f3f4d7bd12ee623f3961c99e.tar.xz | |
Make the IPRs use regular miscreg indexes, and make a table or two to find the miscreg index of a specific IPR.
--HG--
extra : convert_revision : dd235261e7086d6667b1b2bdc4a81b2573e21d53
Diffstat (limited to 'src/arch/alpha/isa')
| -rw-r--r-- | src/arch/alpha/isa/decoder.isa | 16 | ||||
| -rw-r--r-- | src/arch/alpha/isa/main.isa | 1 |
2 files changed, 15 insertions, 2 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 93b941d72..852f483e0 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -745,7 +745,13 @@ decode OPCODE default Unknown::unknown() { 0: OpcdecFault::hw_mfpr(); format HwMoveIPR { 1: hw_mfpr({{ - Ra = xc->readMiscRegWithEffect(ipr_index, fault); + int miscRegIndex = IprToMiscRegIndex[ipr_index]; + if(miscRegIndex < 0 || + (miscRegIndex >= MinWriteOnlyIpr && + miscRegIndex <= MaxWriteOnlyIpr)) + fault = new UnimplementedOpcodeFault; + else + Ra = xc->readMiscRegWithEffect(ipr_index, fault); }}, IsIprAccess); } } @@ -754,7 +760,13 @@ decode OPCODE default Unknown::unknown() { 0: OpcdecFault::hw_mtpr(); format HwMoveIPR { 1: hw_mtpr({{ - xc->setMiscRegWithEffect(ipr_index, Ra); + int miscRegIndex = IprToMiscRegIndex[ipr_index]; + if(miscRegIndex < 0 || + (miscRegIndex >= MinReadOnlyIpr && + miscRegIndex <= MaxWriteOnlyIpr)) + fault = new UnimplementedOpcodeFault; + else + xc->setMiscRegWithEffect(ipr_index, Ra); if (traceData) { traceData->setData(Ra); } }}, IsIprAccess); } diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 1df6ac603..06d3e8243 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -71,6 +71,7 @@ output exec {{ #if FULL_SYSTEM #include "sim/pseudo_inst.hh" #endif +#include "arch/alpha/ipr.hh" #include "base/fenv.hh" #include "config/ss_compatible_fp.hh" #include "cpu/base.hh" |