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authorKevin Lim <ktlim@umich.edu>2006-06-12 19:11:38 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-12 19:11:38 -0400
commitb5cf61efad0acab998b17623ebb00f67cb1f6d50 (patch)
tree5ede96af278766fe300c6c182937ded4eb13ceef /src/arch/alpha/isa
parent6152e8abc3a120efd6c7a86d4299643b5c82b6b1 (diff)
downloadgem5-b5cf61efad0acab998b17623ebb00f67cb1f6d50.tar.xz
Fixes for checker. The RC/RS instructions check the interrupt flag, which isn't verifiable by the checker.
src/arch/alpha/isa/decoder.isa: src/cpu/checker/cpu.cc: Fixes for checker. --HG-- extra : convert_revision : b0ec8f3c4a10453a567cd6691283fc498403795e
Diffstat (limited to 'src/arch/alpha/isa')
-rw-r--r--src/arch/alpha/isa/decoder.isa4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index fab2ca2e1..dd29e47e4 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -659,11 +659,11 @@ decode OPCODE default Unknown::unknown() {
0xe000: rc({{
Ra = xc->readIntrFlag();
xc->setIntrFlag(0);
- }}, IsNonSpeculative);
+ }}, IsNonSpeculative, IsUnverifiable);
0xf000: rs({{
Ra = xc->readIntrFlag();
xc->setIntrFlag(1);
- }}, IsNonSpeculative);
+ }}, IsNonSpeculative, IsUnverifiable);
}
#else
format FailUnimpl {