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authorGabe Black <gblack@eecs.umich.edu>2006-10-31 03:37:01 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-10-31 03:37:01 -0500
commit038217049a952a67f29b79c416a35d89fea31f70 (patch)
tree52b5ba3e01ce3937e3a6733c871f8bc3f8e2d9d9 /src/arch/alpha/isa
parent4862879a9420c52d48532d957b616c458b643a1e (diff)
downloadgem5-038217049a952a67f29b79c416a35d89fea31f70.tar.xz
Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions.
--HG-- extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
Diffstat (limited to 'src/arch/alpha/isa')
-rw-r--r--src/arch/alpha/isa/decoder.isa8
-rw-r--r--src/arch/alpha/isa/main.isa5
2 files changed, 7 insertions, 6 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 5bd19b677..93b941d72 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -661,12 +661,12 @@ decode OPCODE default Unknown::unknown() {
#if FULL_SYSTEM
format BasicOperate {
0xe000: rc({{
- Ra = xc->readIntrFlag();
- xc->setIntrFlag(0);
+ Ra = IntrFlag;
+ IntrFlag = 0;
}}, IsNonSpeculative, IsUnverifiable);
0xf000: rs({{
- Ra = xc->readIntrFlag();
- xc->setIntrFlag(1);
+ Ra = IntrFlag;
+ IntrFlag = 1;
}}, IsNonSpeculative, IsUnverifiable);
}
#else
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 2024b1117..1df6ac603 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -183,8 +183,9 @@ def operands {{
'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
- 'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
- 'FPCR': (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
+ 'Runiq': ('ControlReg', 'uq', 'AlphaISA::Uniq_DepTag', None, 1),
+ 'FPCR': ('ControlReg', 'uq', 'AlphaISA::Fpcr_DepTag', None, 1),
+ 'IntrFlag': ('ControlReg', 'uq', 'AlphaISA::Intr_Flag_DepTag', None, 1),
# The next two are hacks for non-full-system call-pal emulation
'R0': ('IntReg', 'uq', '0', None, 1),
'R16': ('IntReg', 'uq', '16', None, 1),