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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-10-11 02:27:21 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-10-11 02:27:21 -0700 |
| commit | da7209ec93f3cdad11c02906357f06fa29652996 (patch) | |
| tree | 54847aa95a3dc16e94d42f985722b5dac0322ad9 /src/arch/alpha/isa | |
| parent | 3af428606ad35e2cd40d5d1d39010ff732bfee4f (diff) | |
| download | gem5-da7209ec93f3cdad11c02906357f06fa29652996.tar.xz | |
CPU: Eliminate the hwrei function.
Diffstat (limited to 'src/arch/alpha/isa')
| -rw-r--r-- | src/arch/alpha/isa/decoder.isa | 11 | ||||
| -rw-r--r-- | src/arch/alpha/isa/main.isa | 2 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 270940df2..8025ba69f 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -786,7 +786,16 @@ decode OPCODE default Unknown::unknown() { format BasicOperate { 0x1e: decode PALMODE { 0: OpcdecFault::hw_rei(); - 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore); + 1: hw_rei({{ + NPC = ExcAddr; + ThreadContext * tc = xc->tcBase(); + if (!tc->misspeculating()) { + AlphaISA::Kernel::Statistics * kernelStats = + tc->getKernelStats(); + if (kernelStats) + kernelStats->hwrei(); + } + }}, IsSerializing, IsSerializeBefore); } // M5 special opcodes use the reserved 0x01 opcode space diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 5231712c8..078982697 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -69,6 +69,7 @@ output exec {{ #include <math.h> #if FULL_SYSTEM +#include "arch/alpha/kernel_stats.hh" #include "sim/pseudo_inst.hh" #endif #include "arch/alpha/ipr.hh" @@ -187,6 +188,7 @@ def operands {{ 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1), 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1), 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1), + 'ExcAddr': ('ControlReg', 'uq', 'IPR_EXC_ADDR', None, 1), # The next two are hacks for non-full-system call-pal emulation 'R0': ('IntReg', 'uq', '0', None, 1), 'R16': ('IntReg', 'uq', '16', None, 1), |