ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.

By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.

3 files changed, 134 insertions, 134 deletions

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index ce0c92213..106290784 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -41,35 +41,35 @@ decode OPCODE default Unknown::unknown() {
     }
 
     format LoadOrNop {
-        0x0a: ldbu({{ Ra.uq = Mem.ub; }});
-        0x0c: ldwu({{ Ra.uq = Mem.uw; }});
-        0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
-        0x23: ldt({{ Fa = Mem.df; }});
-        0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC);
-        0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC);
+        0x0a: ldbu({{ Ra_uq = Mem_ub; }});
+        0x0c: ldwu({{ Ra_uq = Mem_uw; }});
+        0x0b: ldq_u({{ Ra = Mem_uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
+        0x23: ldt({{ Fa = Mem_df; }});
+        0x2a: ldl_l({{ Ra_sl = Mem_sl; }}, mem_flags = LLSC);
+        0x2b: ldq_l({{ Ra_uq = Mem_uq; }}, mem_flags = LLSC);
     }
 
     format LoadOrPrefetch {
-        0x28: ldl({{ Ra.sl = Mem.sl; }});
-        0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
+        0x28: ldl({{ Ra_sl = Mem_sl; }});
+        0x29: ldq({{ Ra_uq = Mem_uq; }}, pf_flags = EVICT_NEXT);
         // IsFloating flag on lds gets the prefetch to disassemble
         // using f31 instead of r31... funcitonally it's unnecessary
-        0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
+        0x22: lds({{ Fa_uq = s_to_t(Mem_ul); }},
                   pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
     }
 
     format Store {
-        0x0e: stb({{ Mem.ub = Ra<7:0>; }});
-        0x0d: stw({{ Mem.uw = Ra<15:0>; }});
-        0x2c: stl({{ Mem.ul = Ra<31:0>; }});
-        0x2d: stq({{ Mem.uq = Ra.uq; }});
-        0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
-        0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
-        0x27: stt({{ Mem.df = Fa; }});
+        0x0e: stb({{ Mem_ub = Ra<7:0>; }});
+        0x0d: stw({{ Mem_uw = Ra<15:0>; }});
+        0x2c: stl({{ Mem_ul = Ra<31:0>; }});
+        0x2d: stq({{ Mem_uq = Ra_uq; }});
+        0x0f: stq_u({{ Mem_uq = Ra_uq; }}, {{ EA = (Rb + disp) & ~7; }});
+        0x26: sts({{ Mem_ul = t_to_s(Fa_uq); }});
+        0x27: stt({{ Mem_df = Fa; }});
     }
 
     format StoreCond {
-        0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
+        0x2e: stl_c({{ Mem_ul = Ra<31:0>; }},
                     {{
                         uint64_t tmp = write_result;
                         // see stq_c
@@ -78,7 +78,7 @@ decode OPCODE default Unknown::unknown() {
                             xc->setStCondFailures(0);
                         }
                     }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
-        0x2f: stq_c({{ Mem.uq = Ra; }},
+        0x2f: stq_c({{ Mem_uq = Ra; }},
                     {{
                         uint64_t tmp = write_result;
                         // If the write operation returns 0 or 1, then
@@ -102,17 +102,17 @@ decode OPCODE default Unknown::unknown() {
 
         0x10: decode INTFUNC {  // integer arithmetic operations
 
-            0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
+            0x00: addl({{ Rc_sl = Ra_sl + Rb_or_imm_sl; }});
             0x40: addlv({{
-                int32_t tmp  = Ra.sl + Rb_or_imm.sl;
+                int32_t tmp  = Ra_sl + Rb_or_imm_sl;
                 // signed overflow occurs when operands have same sign
                 // and sign of result does not match.
-                if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
+                if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
                     fault = new IntegerOverflowFault;
-                Rc.sl = tmp;
+                Rc_sl = tmp;
             }});
-            0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
-            0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
+            0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }});
+            0x12: s8addl({{ Rc_sl = (Ra_sl << 3) + Rb_or_imm_sl; }});
 
             0x20: addq({{ Rc = Ra + Rb_or_imm; }});
             0x60: addqv({{
@@ -126,19 +126,19 @@ decode OPCODE default Unknown::unknown() {
             0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
             0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
 
-            0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
+            0x09: subl({{ Rc_sl = Ra_sl - Rb_or_imm_sl; }});
             0x49: sublv({{
-                int32_t tmp  = Ra.sl - Rb_or_imm.sl;
+                int32_t tmp  = Ra_sl - Rb_or_imm_sl;
                 // signed overflow detection is same as for add,
                 // except we need to look at the *complemented*
                 // sign bit of the subtrahend (Rb), i.e., if the initial
                 // signs are the *same* then no overflow can occur
-                if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
+                if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
                     fault = new IntegerOverflowFault;
-                Rc.sl = tmp;
+                Rc_sl = tmp;
             }});
-            0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
-            0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
+            0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }});
+            0x1b: s8subl({{ Rc_sl = (Ra_sl << 3) - Rb_or_imm_sl; }});
 
             0x29: subq({{ Rc = Ra - Rb_or_imm; }});
             0x69: subqv({{
@@ -155,17 +155,17 @@ decode OPCODE default Unknown::unknown() {
             0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
 
             0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
-            0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
-            0x4d: cmplt({{ Rc = (Ra.sq <  Rb_or_imm.sq); }});
-            0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
-            0x1d: cmpult({{ Rc = (Ra.uq <  Rb_or_imm.uq); }});
+            0x6d: cmple({{ Rc = (Ra_sq <= Rb_or_imm_sq); }});
+            0x4d: cmplt({{ Rc = (Ra_sq <  Rb_or_imm_sq); }});
+            0x3d: cmpule({{ Rc = (Ra_uq <= Rb_or_imm_uq); }});
+            0x1d: cmpult({{ Rc = (Ra_uq <  Rb_or_imm_uq); }});
 
             0x0f: cmpbge({{
                 int hi = 7;
                 int lo = 0;
                 uint64_t tmp = 0;
                 for (int i = 0; i < 8; ++i) {
-                    tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
+                    tmp |= (Ra_uq<hi:lo> >= Rb_or_imm_uq<hi:lo>) << i;
                     hi += 8;
                     lo += 8;
                 }
@@ -187,10 +187,10 @@ decode OPCODE default Unknown::unknown() {
             0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
             0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
             0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
-            0x44: cmovlt({{ Rc = (Ra.sq <  0) ? Rb_or_imm : Rc; }});
-            0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
-            0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
-            0x66: cmovgt({{ Rc = (Ra.sq >  0) ? Rb_or_imm : Rc; }});
+            0x44: cmovlt({{ Rc = (Ra_sq <  0) ? Rb_or_imm : Rc; }});
+            0x46: cmovge({{ Rc = (Ra_sq >= 0) ? Rb_or_imm : Rc; }});
+            0x64: cmovle({{ Rc = (Ra_sq <= 0) ? Rb_or_imm : Rc; }});
+            0x66: cmovgt({{ Rc = (Ra_sq >  0) ? Rb_or_imm : Rc; }});
 
             // For AMASK, RA must be R31.
             0x61: decode RA {
@@ -214,8 +214,8 @@ decode OPCODE default Unknown::unknown() {
 
         0x12: decode INTFUNC {
             0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
-            0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
-            0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
+            0x34: srl({{ Rc = Ra_uq >> Rb_or_imm<5:0>; }});
+            0x3c: sra({{ Rc = Ra_sq >> Rb_or_imm<5:0>; }});
 
             0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
             0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
@@ -235,10 +235,10 @@ decode OPCODE default Unknown::unknown() {
                 Rc =  bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
             }});
 
-            0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
-            0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
-            0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
-            0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
+            0x06: extbl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
+            0x16: extwl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
+            0x26: extll({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
+            0x36: extql({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8)); }});
 
             0x5a: extwh({{
                 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
@@ -254,15 +254,15 @@ decode OPCODE default Unknown::unknown() {
 
             0x57: inswh({{
                 int bv = Rb_or_imm<2:0>;
-                Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
+                Rc = bv ? (Ra_uq<15:0> >> (64 - 8 * bv)) : 0;
             }});
             0x67: inslh({{
                 int bv = Rb_or_imm<2:0>;
-                Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
+                Rc = bv ? (Ra_uq<31:0> >> (64 - 8 * bv)) : 0;
             }});
             0x77: insqh({{
                 int bv = Rb_or_imm<2:0>;
-                Rc = bv ? (Ra.uq       >> (64 - 8 * bv)) : 0;
+                Rc = bv ? (Ra_uq       >> (64 - 8 * bv)) : 0;
             }});
 
             0x30: zap({{
@@ -284,7 +284,7 @@ decode OPCODE default Unknown::unknown() {
         }
 
         0x13: decode INTFUNC {  // integer multiplies
-            0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
+            0x00: mull({{ Rc_sl = Ra_sl * Rb_or_imm_sl; }}, IntMultOp);
             0x20: mulq({{ Rc    = Ra    * Rb_or_imm;    }}, IntMultOp);
             0x30: umulh({{
                 uint64_t hi, lo;
@@ -293,8 +293,8 @@ decode OPCODE default Unknown::unknown() {
             }}, IntMultOp);
             0x40: mullv({{
                 // 32-bit multiply with trap on overflow
-                int64_t Rax = Ra.sl;    // sign extended version of Ra.sl
-                int64_t Rbx = Rb_or_imm.sl;
+                int64_t Rax = Ra_sl;    // sign extended version of Ra_sl
+                int64_t Rbx = Rb_or_imm_sl;
                 int64_t tmp = Rax * Rbx;
                 // To avoid overflow, all the upper 32 bits must match
                 // the sign bit of the lower 32.  We code this as
@@ -302,7 +302,7 @@ decode OPCODE default Unknown::unknown() {
                 uint64_t sign_bits = tmp<63:31>;
                 if (sign_bits != 0 && sign_bits != mask(33))
                     fault = new IntegerOverflowFault;
-                Rc.sl = tmp<31:0>;
+                Rc_sl = tmp<31:0>;
             }}, IntMultOp);
             0x60: mulqv({{
                 // 64-bit multiply with trap on overflow
@@ -318,8 +318,8 @@ decode OPCODE default Unknown::unknown() {
         }
 
         0x1c: decode INTFUNC {
-            0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
-            0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
+            0x00: decode RA { 31: sextb({{ Rc_sb = Rb_or_imm< 7:0>; }}); }
+            0x01: decode RA { 31: sextw({{ Rc_sw = Rb_or_imm<15:0>; }}); }
 
             0x30: ctpop({{
                              uint64_t count = 0;
@@ -335,8 +335,8 @@ decode OPCODE default Unknown::unknown() {
                              int hi = 7;
                              int lo = 0;
                              for (int i = 0; i < 8; ++i) {
-                                 uint8_t ra_ub = Ra.uq<hi:lo>;
-                                 uint8_t rb_ub = Rb.uq<hi:lo>;
+                                 uint8_t ra_ub = Ra_uq<hi:lo>;
+                                 uint8_t rb_ub = Rb_uq<hi:lo>;
                                  temp += (ra_ub >= rb_ub) ? 
                                          (ra_ub - rb_ub) : (rb_ub - ra_ub);
                                  hi += 8;
@@ -375,25 +375,25 @@ decode OPCODE default Unknown::unknown() {
 
 
             0x34: unpkbw({{ 
-                             Rc = (Rb.uq<7:0> 
-                                   | (Rb.uq<15:8> << 16) 
-                                   | (Rb.uq<23:16> << 32) 
-                                   | (Rb.uq<31:24> << 48)); 
+                             Rc = (Rb_uq<7:0>
+                                   | (Rb_uq<15:8> << 16)
+                                   | (Rb_uq<23:16> << 32)
+                                   | (Rb_uq<31:24> << 48));
                            }}, IntAluOp);
 
             0x35: unpkbl({{
-                             Rc = (Rb.uq<7:0> | (Rb.uq<15:8> << 32)); 
+                             Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 32));
                            }}, IntAluOp);
 
             0x36: pkwb({{
-                             Rc = (Rb.uq<7:0> 
-                                   | (Rb.uq<23:16> << 8) 
-                                   | (Rb.uq<39:32> << 16) 
-                                   | (Rb.uq<55:48> << 24)); 
+                             Rc = (Rb_uq<7:0>
+                                   | (Rb_uq<23:16> << 8)
+                                   | (Rb_uq<39:32> << 16)
+                                   | (Rb_uq<55:48> << 24));
                            }}, IntAluOp);
 
             0x37: pklb({{
-                             Rc = (Rb.uq<7:0> | (Rb.uq<39:32> << 8)); 
+                             Rc = (Rb_uq<7:0> | (Rb_uq<39:32> << 8));
                            }}, IntAluOp);
 
             0x38: minsb8({{
@@ -401,11 +401,11 @@ decode OPCODE default Unknown::unknown() {
                              int hi = 63;
                              int lo = 56;
                              for (int i = 7; i >= 0; --i) {
-                                 int8_t ra_sb = Ra.uq<hi:lo>;
-                                 int8_t rb_sb = Rb.uq<hi:lo>;
+                                 int8_t ra_sb = Ra_uq<hi:lo>;
+                                 int8_t rb_sb = Rb_uq<hi:lo>;
                                  temp = ((temp << 8) 
-                                         | ((ra_sb < rb_sb) ? Ra.uq<hi:lo>
-                                                          : Rb.uq<hi:lo>));
+                                         | ((ra_sb < rb_sb) ? Ra_uq<hi:lo>
+                                                          : Rb_uq<hi:lo>));
                                  hi -= 8;
                                  lo -= 8;
                              }
@@ -417,11 +417,11 @@ decode OPCODE default Unknown::unknown() {
                              int hi = 63;
                              int lo = 48;
                              for (int i = 3; i >= 0; --i) {
-                                 int16_t ra_sw = Ra.uq<hi:lo>;
-                                 int16_t rb_sw = Rb.uq<hi:lo>;
+                                 int16_t ra_sw = Ra_uq<hi:lo>;
+                                 int16_t rb_sw = Rb_uq<hi:lo>;
                                  temp = ((temp << 16) 
-                                         | ((ra_sw < rb_sw) ? Ra.uq<hi:lo>
-                                                          : Rb.uq<hi:lo>));
+                                         | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
+                                                          : Rb_uq<hi:lo>));
                                  hi -= 16;
                                  lo -= 16;
                              }
@@ -433,11 +433,11 @@ decode OPCODE default Unknown::unknown() {
                              int hi = 63;
                              int lo = 56;
                              for (int i = 7; i >= 0; --i) {
-                                 uint8_t ra_ub = Ra.uq<hi:lo>;
-                                 uint8_t rb_ub = Rb.uq<hi:lo>;
+                                 uint8_t ra_ub = Ra_uq<hi:lo>;
+                                 uint8_t rb_ub = Rb_uq<hi:lo>;
                                  temp = ((temp << 8) 
-                                         | ((ra_ub < rb_ub) ? Ra.uq<hi:lo>
-                                                          : Rb.uq<hi:lo>));
+                                         | ((ra_ub < rb_ub) ? Ra_uq<hi:lo>
+                                                          : Rb_uq<hi:lo>));
                                  hi -= 8;
                                  lo -= 8;
                              }
@@ -449,11 +449,11 @@ decode OPCODE default Unknown::unknown() {
                              int hi = 63;
                              int lo = 48;
                              for (int i = 3; i >= 0; --i) {
-                                 uint16_t ra_sw = Ra.uq<hi:lo>;
-                                 uint16_t rb_sw = Rb.uq<hi:lo>;
+                                 uint16_t ra_sw = Ra_uq<hi:lo>;
+                                 uint16_t rb_sw = Rb_uq<hi:lo>;
                                  temp = ((temp << 16) 
-                                         | ((ra_sw < rb_sw) ? Ra.uq<hi:lo>
-                                                          : Rb.uq<hi:lo>));
+                                         | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
+                                                          : Rb_uq<hi:lo>));
                                  hi -= 16;
                                  lo -= 16;
                              }
@@ -465,11 +465,11 @@ decode OPCODE default Unknown::unknown() {
                              int hi = 63;
                              int lo = 56;
                              for (int i = 7; i >= 0; --i) {
-                                 uint8_t ra_ub = Ra.uq<hi:lo>;
-                                 uint8_t rb_ub = Rb.uq<hi:lo>;
+                                 uint8_t ra_ub = Ra_uq<hi:lo>;
+                                 uint8_t rb_ub = Rb_uq<hi:lo>;
                                  temp = ((temp << 8) 
-                                         | ((ra_ub > rb_ub) ? Ra.uq<hi:lo>
-                                                          : Rb.uq<hi:lo>));
+                                         | ((ra_ub > rb_ub) ? Ra_uq<hi:lo>
+                                                          : Rb_uq<hi:lo>));
                                  hi -= 8;
                                  lo -= 8;
                              }
@@ -481,11 +481,11 @@ decode OPCODE default Unknown::unknown() {
                              int hi = 63;
                              int lo = 48;
                              for (int i = 3; i >= 0; --i) {
-                                 uint16_t ra_uw = Ra.uq<hi:lo>;
-                                 uint16_t rb_uw = Rb.uq<hi:lo>;
+                                 uint16_t ra_uw = Ra_uq<hi:lo>;
+                                 uint16_t rb_uw = Rb_uq<hi:lo>;
                                  temp = ((temp << 16) 
-                                         | ((ra_uw > rb_uw) ? Ra.uq<hi:lo>
-                                                          : Rb.uq<hi:lo>));
+                                         | ((ra_uw > rb_uw) ? Ra_uq<hi:lo>
+                                                          : Rb_uq<hi:lo>));
                                  hi -= 16;
                                  lo -= 16;
                              }
@@ -497,11 +497,11 @@ decode OPCODE default Unknown::unknown() {
                              int hi = 63;
                              int lo = 56;
                              for (int i = 7; i >= 0; --i) {
-                                 int8_t ra_sb = Ra.uq<hi:lo>;
-                                 int8_t rb_sb = Rb.uq<hi:lo>;
+                                 int8_t ra_sb = Ra_uq<hi:lo>;
+                                 int8_t rb_sb = Rb_uq<hi:lo>;
                                  temp = ((temp << 8) 
-                                         | ((ra_sb > rb_sb) ? Ra.uq<hi:lo>
-                                                          : Rb.uq<hi:lo>));
+                                         | ((ra_sb > rb_sb) ? Ra_uq<hi:lo>
+                                                          : Rb_uq<hi:lo>));
                                  hi -= 8;
                                  lo -= 8;
                              }
@@ -513,11 +513,11 @@ decode OPCODE default Unknown::unknown() {
                              int hi = 63;
                              int lo = 48;
                              for (int i = 3; i >= 0; --i) {
-                                 int16_t ra_sw = Ra.uq<hi:lo>;
-                                 int16_t rb_sw = Rb.uq<hi:lo>;
+                                 int16_t ra_sw = Ra_uq<hi:lo>;
+                                 int16_t rb_sw = Rb_uq<hi:lo>;
                                  temp = ((temp << 16) 
-                                         | ((ra_sw > rb_sw) ? Ra.uq<hi:lo>
-                                                          : Rb.uq<hi:lo>));
+                                         | ((ra_sw > rb_sw) ? Ra_uq<hi:lo>
+                                                          : Rb_uq<hi:lo>));
                                  hi -= 16;
                                  lo -= 16;
                              }
@@ -526,10 +526,10 @@ decode OPCODE default Unknown::unknown() {
 
             format BasicOperateWithNopCheck {
                 0x70: decode RB {
-                    31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
+                    31: ftoit({{ Rc = Fa_uq; }}, FloatCvtOp);
                 }
                 0x78: decode RB {
-                    31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
+                    31: ftois({{ Rc_sl = t_to_s(Fa_uq); }},
                               FloatCvtOp);
                 }
             }
@@ -540,10 +540,10 @@ decode OPCODE default Unknown::unknown() {
     format CondBranch {
         0x39: beq({{ cond = (Ra == 0); }});
         0x3d: bne({{ cond = (Ra != 0); }});
-        0x3e: bge({{ cond = (Ra.sq >= 0); }});
-        0x3f: bgt({{ cond = (Ra.sq >  0); }});
-        0x3b: ble({{ cond = (Ra.sq <= 0); }});
-        0x3a: blt({{ cond = (Ra.sq < 0); }});
+        0x3e: bge({{ cond = (Ra_sq >= 0); }});
+        0x3f: bgt({{ cond = (Ra_sq >  0); }});
+        0x3b: ble({{ cond = (Ra_sq <= 0); }});
+        0x3a: blt({{ cond = (Ra_sq < 0); }});
         0x38: blbc({{ cond = ((Ra & 1) == 0); }});
         0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
 
@@ -577,8 +577,8 @@ decode OPCODE default Unknown::unknown() {
         0x4: decode RB {
             31: decode FP_FULLFUNC {
                 format BasicOperateWithNopCheck {
-                    0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
-                    0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
+                    0x004: itofs({{ Fc_uq = s_to_t(Ra_ul); }}, FloatCvtOp);
+                    0x024: itoft({{ Fc_uq = Ra_uq; }}, FloatCvtOp);
                     0x014: FailUnimpl::itoff(); // VAX-format conversion
                 }
             }
@@ -596,9 +596,9 @@ decode OPCODE default Unknown::unknown() {
                     }}, FloatSqrtOp);
 #else
                     0x0b: sqrts({{
-                        if (Fb.sf < 0.0)
+                        if (Fb_sf < 0.0)
                             fault = new ArithmeticFault;
-                        Fc.sf = sqrt(Fb.sf);
+                        Fc_sf = sqrt(Fb_sf);
                     }}, FloatSqrtOp);
 #endif
                     0x2b: sqrtt({{
@@ -638,10 +638,10 @@ decode OPCODE default Unknown::unknown() {
                        0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
                        0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
 #else
-                       0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
-                       0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
-                       0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
-                       0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
+                       0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }});
+                       0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }});
+                       0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp);
+                       0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp);
 #endif
 
                        0x20: addt({{ Fc = Fa + Fb; }});
@@ -681,13 +681,13 @@ decode OPCODE default Unknown::unknown() {
                     0x2f: decode FP_ROUNDMODE {
                         format FPFixedRounding {
                             // "chopped" i.e. round toward zero
-                            0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
+                            0: cvttq({{ Fc_sq = (int64_t)trunc(Fb); }},
                                      Chopped);
                             // round to minus infinity
-                            1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
+                            1: cvttq({{ Fc_sq = (int64_t)floor(Fb); }},
                                      MinusInfinity);
                         }
-                      default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
+                      default: cvttq({{ Fc_sq = (int64_t)nearbyint(Fb); }});
                     }
 
                     // The cvtts opcode is overloaded to be cvtst if the trap
@@ -696,9 +696,9 @@ decode OPCODE default Unknown::unknown() {
                         format BasicOperateWithNopCheck {
                             // trap on denorm version "cvtst/s" is
                             // simulated same as cvtst
-                            0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
+                            0x2ac, 0x6ac: cvtst({{ Fc = Fb_sf; }});
                         }
-                      default: cvtts({{ Fc.sf = Fb; }});
+                      default: cvtts({{ Fc_sf = Fb; }});
                     }
 
                     // The trapping mode for integer-to-FP conversions
@@ -706,10 +706,10 @@ decode OPCODE default Unknown::unknown() {
                     // allowed.  The full set of rounding modes are
                     // supported though.
                     0x3c: decode FP_TRAPMODE {
-                        0,7: cvtqs({{ Fc.sf = Fb.sq; }});
+                        0,7: cvtqs({{ Fc_sf = Fb_sq; }});
                     }
                     0x3e: decode FP_TRAPMODE {
-                        0,7: cvtqt({{ Fc    = Fb.sq; }});
+                        0,7: cvtqt({{ Fc    = Fb_sq; }});
                     }
                 }
             }
@@ -720,10 +720,10 @@ decode OPCODE default Unknown::unknown() {
     0x17: decode FP_FULLFUNC {
         format BasicOperateWithNopCheck {
             0x010: cvtlq({{
-                Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
+                Fc_sl = (Fb_uq<63:62> << 30) | Fb_uq<58:29>;
             }});
             0x030: cvtql({{
-                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
+                Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
             }});
 
             // We treat the precise & imprecise trapping versions of
@@ -732,20 +732,20 @@ decode OPCODE default Unknown::unknown() {
                 // To avoid overflow, all the upper 32 bits must match
                 // the sign bit of the lower 32.  We code this as
                 // checking the upper 33 bits for all 0s or all 1s.
-                uint64_t sign_bits = Fb.uq<63:31>;
+                uint64_t sign_bits = Fb_uq<63:31>;
                 if (sign_bits != 0 && sign_bits != mask(33))
                     fault = new IntegerOverflowFault;
-                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
+                Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
             }});
 
             0x020: cpys({{  // copy sign
-                Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
+                Fc_uq = (Fa_uq<63:> << 63) | Fb_uq<62:0>;
             }});
             0x021: cpysn({{ // copy sign negated
-                Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
+                Fc_uq = (~Fa_uq<63:> << 63) | Fb_uq<62:0>;
             }});
             0x022: cpyse({{ // copy sign and exponent
-                Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
+                Fc_uq = (Fa_uq<63:52> << 52) | Fb_uq<51:0>;
             }});
 
             0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
@@ -755,8 +755,8 @@ decode OPCODE default Unknown::unknown() {
             0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
             0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
 
-            0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
-            0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
+            0x024: mt_fpcr({{ FPCR = Fa_uq; }}, IsIprAccess);
+            0x025: mf_fpcr({{ Fa_uq = FPCR; }}, IsIprAccess);
         }
     }
 
@@ -862,9 +862,9 @@ decode OPCODE default Unknown::unknown() {
         0: OpcdecFault::hw_st_quad();
         1: decode HW_LDST_QUAD {
             format HwLoad {
-                0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }},
+                0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }},
                          L, IsSerializing, IsSerializeBefore);
-                1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }},
+                1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }},
                          Q, IsSerializing, IsSerializeBefore);
             }
         }
@@ -876,9 +876,9 @@ decode OPCODE default Unknown::unknown() {
             1: decode HW_LDST_COND {
                 0: decode HW_LDST_QUAD {
                     0: hw_st({{ EA = (Rb + disp) & ~3; }},
-                {{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
+                {{ Mem_ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
                     1: hw_st({{ EA = (Rb + disp) & ~7; }},
-                {{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore);
+                {{ Mem_uq = Ra_uq; }}, Q, IsSerializing, IsSerializeBefore);
                 }
 
                 1: FailUnimpl::hw_st_cond();
diff --git a/src/arch/alpha/isa/int.isa b/src/arch/alpha/isa/int.isa
index bd9c3ccd9..265b3c4a9 100644
--- a/src/arch/alpha/isa/int.isa
+++ b/src/arch/alpha/isa/int.isa
@@ -110,7 +110,7 @@ def format IntegerOperate(code, *opt_flags) {{
         # generate immediate version by substituting 'imm'
         # note that imm takes no extenstion, so we extend
         # the regexp to replace any extension as well
-        imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
+        imm_code = re.sub(r'Rb_or_imm(_\w+)?', 'imm', orig_code)
 
     # generate declaration for register version
     iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_flags)
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 3d80ddf68..796c5e38e 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -176,7 +176,7 @@ def operand_types {{
 def operands {{
     # Int regs default to unsigned, but code should not count on this.
     # For clarity, descriptions that depend on unsigned behavior should
-    # explicitly specify '.uq'.
+    # explicitly specify '_uq'.
     'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
            'IsInteger', 1),
     'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',