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authorKorey Sewell <ksewell@umich.edu>2009-05-12 15:01:13 -0400
committerKorey Sewell <ksewell@umich.edu>2009-05-12 15:01:13 -0400
commit1c8dfd92543aba5f49e464b17e7e8143fc01a58c (patch)
tree3c5b9059b07e8d0bccdf826249330bfcb8c5c1cc /src/arch/alpha/isa
parent63db33c4b1cd7a071c2a2fe47bda21a73618d054 (diff)
downloadgem5-1c8dfd92543aba5f49e464b17e7e8143fc01a58c.tar.xz
inorder-alpha-port: initial inorder support of ALPHA
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions * * * Remove namespace from header file. Causes compiler issues that are hard to find * * * Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time * * * Expose memory access size and flags through instruction object (temporarily memAccSize and memFlags to get TLB stuff working.)
Diffstat (limited to 'src/arch/alpha/isa')
-rw-r--r--src/arch/alpha/isa/mem.isa39
1 files changed, 38 insertions, 1 deletions
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index cd5e117ec..9a8503637 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -65,6 +65,8 @@ output header {{
const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
const StaticInstPtr &memAccInst() const { return memAccPtr; }
+
+ Request::Flags memAccFlags() { return memAccessFlags; }
};
/**
@@ -176,6 +178,8 @@ def template LoadStoreDeclare {{
%(InitiateAccDeclare)s
%(CompleteAccDeclare)s
+
+ %(MemAccSizeDeclare)s
};
}};
@@ -190,6 +194,25 @@ def template CompleteAccDeclare {{
Trace::InstRecord *) const;
}};
+def template MemAccSizeDeclare {{
+ int memAccSize(%(CPU_exec_context)s *xc);
+}};
+
+def template MiscMemAccSize {{
+ int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+ {
+ panic("Misc instruction does not support split access method!");
+ return 0;
+ }
+}};
+
+def template LoadStoreMemAccSize {{
+ int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+ {
+ // Return the memory access size in bytes
+ return (%(mem_acc_size)d / 8);
+ }
+}};
def template EACompConstructor {{
/** TODO: change op_class to AddrGenOp or something (requires
@@ -620,6 +643,14 @@ def template MiscCompleteAcc {{
}
}};
+def template MiscMemAccSize {{
+ int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+ {
+ panic("Misc instruction does not support split access method!");
+ return 0;
+ }
+}};
+
// load instructions use Ra as dest, so check for
// Ra == 31 to detect nops
def template LoadNopCheckDecode {{
@@ -693,6 +724,11 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
+ if (exec_template_base == 'Load' or exec_template_base == 'Store'):
+ memAccSizeTemplate = eval('LoadStoreMemAccSize')
+ else:
+ memAccSizeTemplate = eval('MiscMemAccSize')
+
# (header_output, decoder_output, decode_block, exec_output)
return (LoadStoreDeclare.subst(iop),
EACompConstructor.subst(ea_iop)
@@ -703,7 +739,8 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ memAccExecTemplate.subst(memacc_iop)
+ fullExecTemplate.subst(iop)
+ initiateAccTemplate.subst(iop)
- + completeAccTemplate.subst(iop))
+ + completeAccTemplate.subst(iop)
+ + memAccSizeTemplate.subst(memacc_iop))
}};
def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},