summaryrefslogtreecommitdiff
path: root/src/arch/alpha/isa
diff options
context:
space:
mode:
authorNathanael Premillieu <nathanael.premillieu@arm.com>2017-04-05 12:46:06 -0500
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-07-05 14:43:49 +0000
commit5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch)
tree7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/arch/alpha/isa
parent864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff)
downloadgem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/arch/alpha/isa')
-rw-r--r--src/arch/alpha/isa/branch.isa2
-rw-r--r--src/arch/alpha/isa/fp.isa2
-rw-r--r--src/arch/alpha/isa/main.isa17
3 files changed, 7 insertions, 14 deletions
diff --git a/src/arch/alpha/isa/branch.isa b/src/arch/alpha/isa/branch.isa
index b60cb6d1e..d4b6db043 100644
--- a/src/arch/alpha/isa/branch.isa
+++ b/src/arch/alpha/isa/branch.isa
@@ -130,7 +130,7 @@ output decoder {{
Jump::branchTarget(ThreadContext *tc) const
{
PCState pc = tc->pcState();
- uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
+ uint64_t Rb = tc->readIntReg(_srcRegIdx[0].regIdx);
pc.set((Rb & ~3) | (pc.pc() & 1));
return pc;
}
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index 4d19f1421..afece988f 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -149,7 +149,7 @@ output decoder {{
#ifndef SS_COMPATIBLE_DISASSEMBLY
std::string suffix("");
- suffix += ((_destRegIdx[0] >= FP_Reg_Base)
+ suffix += ((_destRegIdx[0].regClass == FloatRegClass)
? fpTrappingModeSuffix[trappingMode]
: intTrappingModeSuffix[trappingMode]);
suffix += roundingModeSuffix[roundingMode];
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index a1d0de1d6..e75cec524 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -220,13 +220,6 @@ output header {{
{
protected:
- /// Make AlphaISA register dependence tags directly visible in
- /// this class and derived classes. Maybe these should really
- /// live here and not in the AlphaISA namespace.
- enum DependenceTags {
- FP_Reg_Base = AlphaISA::FP_Reg_Base
- };
-
/// Constructor.
AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
OpClass __opClass)
@@ -236,7 +229,7 @@ output header {{
/// Print a register name for disassembly given the unique
/// dependence tag number (FP or int).
- void printReg(std::ostream &os, int reg) const;
+ void printReg(std::ostream &os, RegId reg) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -251,13 +244,13 @@ output header {{
output decoder {{
void
- AlphaStaticInst::printReg(std::ostream &os, int reg) const
+ AlphaStaticInst::printReg(std::ostream &os, RegId reg) const
{
- if (reg < FP_Reg_Base) {
- ccprintf(os, "r%d", reg);
+ if (reg.regClass == IntRegClass) {
+ ccprintf(os, "r%d", reg.regIdx);
}
else {
- ccprintf(os, "f%d", reg - FP_Reg_Base);
+ ccprintf(os, "f%d", reg.regIdx);
}
}