summaryrefslogtreecommitdiff
path: root/src/arch/alpha/isa
diff options
context:
space:
mode:
authorAli Saidi <saidi@eecs.umich.edu>2007-02-21 21:06:17 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-02-21 21:06:17 -0500
commit7a2ecf9e268bf10fc0a2406f3a928a661e97b5fd (patch)
tree6ed93c5595ee96386bfea26b5ac5b87c46f706fb /src/arch/alpha/isa
parenta329631edbf18d01f5f84b57147bdd69f1e2e6b3 (diff)
downloadgem5-7a2ecf9e268bf10fc0a2406f3a928a661e97b5fd.tar.xz
add pseduo instruction support for sparc
util/m5/Makefile.alpha: Clean up to make it a bit easier to muck with util/m5/Makefile.alpha: Make the makefile more reasonable util/m5/Makefile.alpha: Remove authors from copyright. util/m5/Makefile.alpha: Updated Authors from bk prs info util/m5/Makefile.alpha: bk cp Makefile Makefile.alpha src/arch/sparc/tlb.cc: Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate src/arch/alpha/isa/decoder.isa: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: Rename AlphaPseudo -> PseudoInst since it's all generic src/arch/sparc/isa/bitfields.isa: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/includes.isa: src/arch/sparc/isa/operands.isa: Add support for pseudo instructions in sparc util/m5/Makefile.alpha: util/m5/Makefile.sparc: split off alpha make file and sparc make file for m5 app util/m5/m5.c: ivle and ivlb aren't used anymore util/m5/m5op.h: stdint seems like a more generic better fit here util/m5/m5op_alpha.S: move the op ids into their own header file since we can share them between sparc and alpha --HG-- rename : util/m5/Makefile => util/m5/Makefile.sparc rename : util/m5/m5op.S => util/m5/m5op_alpha.S extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834
Diffstat (limited to 'src/arch/alpha/isa')
-rw-r--r--src/arch/alpha/isa/decoder.isa36
1 files changed, 18 insertions, 18 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 1da6a60f1..49c25c3c2 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -790,19 +790,19 @@ decode OPCODE default Unknown::unknown() {
// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {
0x00: arm({{
- AlphaPseudo::arm(xc->tcBase());
+ PseudoInst::arm(xc->tcBase());
}}, IsNonSpeculative);
0x01: quiesce({{
- AlphaPseudo::quiesce(xc->tcBase());
+ PseudoInst::quiesce(xc->tcBase());
}}, IsNonSpeculative, IsQuiesce);
0x02: quiesceNs({{
- AlphaPseudo::quiesceNs(xc->tcBase(), R16);
+ PseudoInst::quiesceNs(xc->tcBase(), R16);
}}, IsNonSpeculative, IsQuiesce);
0x03: quiesceCycles({{
- AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
+ PseudoInst::quiesceCycles(xc->tcBase(), R16);
}}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
0x04: quiesceTime({{
- R0 = AlphaPseudo::quiesceTime(xc->tcBase());
+ R0 = PseudoInst::quiesceTime(xc->tcBase());
}}, IsNonSpeculative, IsUnverifiable);
0x10: ivlb({{
warn_once("Obsolete M5 instruction ivlb encountered.\n");
@@ -811,47 +811,47 @@ decode OPCODE default Unknown::unknown() {
warn_once("Obsolete M5 instruction ivlb encountered.\n");
}});
0x20: m5exit_old({{
- AlphaPseudo::m5exit_old(xc->tcBase());
+ PseudoInst::m5exit_old(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x21: m5exit({{
- AlphaPseudo::m5exit(xc->tcBase(), R16);
+ PseudoInst::m5exit(xc->tcBase(), R16);
}}, No_OpClass, IsNonSpeculative);
0x31: loadsymbol({{
- AlphaPseudo::loadsymbol(xc->tcBase());
+ PseudoInst::loadsymbol(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
0x40: resetstats({{
- AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
+ PseudoInst::resetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x41: dumpstats({{
- AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
+ PseudoInst::dumpstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x42: dumpresetstats({{
- AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17);
+ PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x43: m5checkpoint({{
- AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17);
+ PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x50: m5readfile({{
- R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18);
+ R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
}}, IsNonSpeculative);
0x51: m5break({{
- AlphaPseudo::debugbreak(xc->tcBase());
+ PseudoInst::debugbreak(xc->tcBase());
}}, IsNonSpeculative);
0x52: m5switchcpu({{
- AlphaPseudo::switchcpu(xc->tcBase());
+ PseudoInst::switchcpu(xc->tcBase());
}}, IsNonSpeculative);
0x53: m5addsymbol({{
- AlphaPseudo::addsymbol(xc->tcBase(), R16, R17);
+ PseudoInst::addsymbol(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x54: m5panic({{
panic("M5 panic instruction called at pc=%#x.", xc->readPC());
}}, IsNonSpeculative);
0x55: m5anBegin({{
- AlphaPseudo::anBegin(xc->tcBase(), R16);
+ PseudoInst::anBegin(xc->tcBase(), R16);
}}, IsNonSpeculative);
0x56: m5anWait({{
- AlphaPseudo::anWait(xc->tcBase(), R16, R17);
+ PseudoInst::anWait(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
}
}