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author | Nathan Binkert <nate@binkert.org> | 2007-07-26 23:15:49 -0700 |
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committer | Nathan Binkert <nate@binkert.org> | 2007-07-26 23:15:49 -0700 |
commit | f0fef8f850b0c5aa73337ca11b26169163b2b2e1 (patch) | |
tree | d49d3492618ee85717554cddbe62cba1b5e7fb9c /src/arch/alpha/isa_traits.hh | |
parent | 6b73ff43ff58502c80050c7aeff5a08a4ce61f87 (diff) | |
parent | cda354b07035f73a3b220f89014721300d36a815 (diff) | |
download | gem5-f0fef8f850b0c5aa73337ca11b26169163b2b2e1.tar.xz |
Merge python and x86 changes with cache branch
--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233
Diffstat (limited to 'src/arch/alpha/isa_traits.hh')
-rw-r--r-- | src/arch/alpha/isa_traits.hh | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh index a267ac034..7dc7e5151 100644 --- a/src/arch/alpha/isa_traits.hh +++ b/src/arch/alpha/isa_traits.hh @@ -156,14 +156,12 @@ namespace AlphaISA const int ReturnAddressReg = 26; const int ReturnValueReg = 0; const int FramePointerReg = 15; - const int ArgumentReg0 = 16; - const int ArgumentReg1 = 17; - const int ArgumentReg2 = 18; - const int ArgumentReg3 = 19; - const int ArgumentReg4 = 20; - const int ArgumentReg5 = 21; + + const int ArgumentReg[] = {16, 17, 18, 19, 20, 21}; + const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); + const int SyscallNumReg = ReturnValueReg; - const int SyscallPseudoReturnReg = ArgumentReg4; + const int SyscallPseudoReturnReg = ArgumentReg[4]; const int SyscallSuccessReg = 19; const int LogVMPageSize = 13; // 8K bytes |