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author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
commit | 537239b278f7b8171d2eb09ef7f99c332266c48f (patch) | |
tree | 31984b63cc542f0a57ca96262477575ab0130c09 /src/arch/alpha/isa_traits.hh | |
parent | f738afb865cd82487d6300259d6e87fb50660d2a (diff) | |
download | gem5-537239b278f7b8171d2eb09ef7f99c332266c48f.tar.xz |
Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
Diffstat (limited to 'src/arch/alpha/isa_traits.hh')
-rw-r--r-- | src/arch/alpha/isa_traits.hh | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh index 7dc7e5151..53eea5f69 100644 --- a/src/arch/alpha/isa_traits.hh +++ b/src/arch/alpha/isa_traits.hh @@ -63,14 +63,13 @@ namespace AlphaISA const Addr PageMask = ~(PageBytes - 1); const Addr PageOffset = PageBytes - 1; -#if FULL_SYSTEM //////////////////////////////////////////////////////////////////////// // // Translation stuff // - const Addr PteShift = 3; + const Addr PteShift = 3; const Addr NPtePageShift = PageShift - PteShift; const Addr NPtePage = ULL(1) << NPtePageShift; const Addr PteMask = NPtePage - 1; @@ -90,6 +89,8 @@ namespace AlphaISA // For loading... XXX This maybe could be USegEnd?? --ali const Addr LoadAddrMask = ULL(0xffffffffff); +#if FULL_SYSTEM + //////////////////////////////////////////////////////////////////////// // // Interrupt levels @@ -114,6 +115,8 @@ namespace AlphaISA NumInterruptLevels = INTLEVEL_EXTERNAL_MAX }; +#endif + // EV5 modes enum mode_type { @@ -124,8 +127,6 @@ namespace AlphaISA mode_number // number of modes }; -#endif - // Constants Related to the number of registers const int NumIntArchRegs = 32; |