rename store conditional stuff as extra data so it can be used for conditional swaps as well

Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic

src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
    rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
    add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
    Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
    Make atomic memory ops atomic
    Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
    add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
    remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
    swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
    add a post access code block
src/arch/sparc/isa/includes.isa:
    need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
    add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
    add support for twinloads
    add support for swap and conditional swap instructions
    rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
    Add support for atomic swap memory commands
src/mem/packet_access.hh:
    Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
    Add support for atomic swap memory commands
    Rename sc code to extradata

--HG--
extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656

1 files changed, 2 insertions, 2 deletions

diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index 52fe24173..44b002c6c 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -60,7 +60,7 @@ handleLockedWrite(XC *xc, Request *req)
     if (req->isUncacheable()) {
         // Funky Turbolaser mailbox access...don't update
         // result register (see stq_c in decoder.isa)
-        req->setScResult(2);
+        req->setExtraData(2);
     } else {
         // standard store conditional
         bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
@@ -68,7 +68,7 @@ handleLockedWrite(XC *xc, Request *req)
         if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
             // Lock flag not set or addr mismatch in CPU;
             // don't even bother sending to memory system
-            req->setScResult(0);
+            req->setExtraData(0);
             xc->setMiscReg(MISCREG_LOCKFLAG, false);
             // the rest of this code is not architectural;
             // it's just a debugging aid to help detect