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authorSteve Reinhardt <stever@eecs.umich.edu>2007-02-12 09:27:32 -0800
committerSteve Reinhardt <stever@eecs.umich.edu>2007-02-12 09:27:32 -0800
commitad17b3265178deacb2dce7a98033575c0e98f518 (patch)
treefb837d9a9afa07d4167e94a7920d34a42a3e0171 /src/arch/alpha/locked_mem.hh
parentda1ad46482d80ae45982dc23c09ff13e5d490087 (diff)
parentf78bc80bd75f6f4ebf080620b3aaeaee3b3e46cc (diff)
downloadgem5-ad17b3265178deacb2dce7a98033575c0e98f518.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head --HG-- extra : convert_revision : 496428e23050122a8a0029e5fddea261bef5729e
Diffstat (limited to 'src/arch/alpha/locked_mem.hh')
-rw-r--r--src/arch/alpha/locked_mem.hh8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index 52fe24173..be5086bd7 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -35,6 +35,14 @@
* @file
*
* ISA-specific helper functions for locked memory accesses.
+ *
+ * Note that these functions are not embedded in the ISA description
+ * because they operate on the *physical* address rather than the
+ * virtual address. In the current M5 design, the physical address is
+ * not accessible from the ISA description, only from the CPU model.
+ * Thus the CPU is responsible for calling back to the ISA (here)
+ * after the address translation has been performed to allow the ISA
+ * to do these manipulations based on the physical address.
*/
#include "arch/alpha/miscregfile.hh"