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authorNathan Binkert <nate@binkert.org>2009-05-26 09:23:13 -0700
committerNathan Binkert <nate@binkert.org>2009-05-26 09:23:13 -0700
commit47877cf2dbd6ee2f1cf9b2c609d37b0589e876ca (patch)
tree6beb00dfe7e31b9bf82f7aba4710b0c487b6543f /src/arch/alpha/miscregfile.cc
parentd93392df28fc6c9a5c70fb6252a12afdc72d9344 (diff)
downloadgem5-47877cf2dbd6ee2f1cf9b2c609d37b0589e876ca.tar.xz
types: add a type for thread IDs and try to use it everywhere
Diffstat (limited to 'src/arch/alpha/miscregfile.cc')
-rw-r--r--src/arch/alpha/miscregfile.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc
index 5dc316a83..d52d900fd 100644
--- a/src/arch/alpha/miscregfile.cc
+++ b/src/arch/alpha/miscregfile.cc
@@ -65,7 +65,7 @@ MiscRegFile::MiscRegFile(BaseCPU *_cpu)
MiscReg
-MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid )
+MiscRegFile::readRegNoEffect(int misc_reg, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -85,7 +85,7 @@ MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid )
}
MiscReg
-MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid )
+MiscRegFile::readReg(int misc_reg, ThreadContext *tc, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -104,7 +104,7 @@ MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid )
}
void
-MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid)
+MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -131,7 +131,7 @@ MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid)
void
MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
- unsigned tid)
+ ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR: