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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 15:04:44 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 15:04:44 -0500 |
| commit | 49527ab55312bf02dfce20c45db8f173b0c2324e (patch) | |
| tree | b9212b195a7b253940aaaab5c8b9ef27e43d026e /src/arch/alpha/miscregfile.cc | |
| parent | ea7bdf9f60c404761dfc568d5291c75747a2dd88 (diff) | |
| parent | 689cab36c90b56b3c8a7cda16d758acdd89f9de1 (diff) | |
| download | gem5-49527ab55312bf02dfce20c45db8f173b0c2324e.tar.xz | |
Merge zizzer:/bk/newmem
into zeep.pool:/tmp/newmem
--HG--
extra : convert_revision : f078a05729b5fe464a06a58bc4adcb374f560572
Diffstat (limited to 'src/arch/alpha/miscregfile.cc')
| -rw-r--r-- | src/arch/alpha/miscregfile.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc index 67f6c98e4..1af97adcf 100644 --- a/src/arch/alpha/miscregfile.cc +++ b/src/arch/alpha/miscregfile.cc @@ -61,7 +61,7 @@ namespace AlphaISA } MiscReg - MiscRegFile::readReg(int misc_reg) + MiscRegFile::readRegNoEffect(int misc_reg) { switch(misc_reg) { case MISCREG_FPCR: @@ -87,7 +87,7 @@ namespace AlphaISA } MiscReg - MiscRegFile::readRegWithEffect(int misc_reg, ThreadContext *tc) + MiscRegFile::readReg(int misc_reg, ThreadContext *tc) { switch(misc_reg) { case MISCREG_FPCR: @@ -112,7 +112,7 @@ namespace AlphaISA } void - MiscRegFile::setReg(int misc_reg, const MiscReg &val) + MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val) { switch(misc_reg) { case MISCREG_FPCR: @@ -143,7 +143,7 @@ namespace AlphaISA } void - MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val, + MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc) { switch(misc_reg) { |