diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-14 15:23:23 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-14 15:23:23 -0500 |
| commit | ac2c7967f69e3ffd29a1ed04a15838073dc060de (patch) | |
| tree | d24dc27dcb11414775d2971b645ef4a6fbb922d9 /src/arch/alpha/miscregfile.cc | |
| parent | bc4d15ddd199420d2201fd0e8bde399e51ea0d3d (diff) | |
| parent | 2f6a9454d13e44faba55b14d958f20a04bc36246 (diff) | |
| download | gem5-ac2c7967f69e3ffd29a1ed04a15838073dc060de.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem/
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
--HG--
extra : convert_revision : 966246877ac1f1e6c2675d413b0b405cccfecbeb
Diffstat (limited to 'src/arch/alpha/miscregfile.cc')
| -rw-r--r-- | src/arch/alpha/miscregfile.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc index 4cf57a690..962d4609f 100644 --- a/src/arch/alpha/miscregfile.cc +++ b/src/arch/alpha/miscregfile.cc @@ -132,7 +132,6 @@ namespace AlphaISA MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val, ThreadContext *tc) { -#if FULL_SYSTEM switch(misc_reg) { case MISCREG_FPCR: fpcr = val; @@ -150,12 +149,13 @@ namespace AlphaISA intr_flag = val; return; default: - return setIpr(misc_reg, val, tc); - } +#if FULL_SYSTEM + setIpr(misc_reg, val, tc); #else - //panic("No registers with side effects in SE mode!"); - return; + panic("No registers with side effects in SE mode!"); #endif + return; + } } } |