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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:13 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:13 -0400 |
| commit | 1c8dfd92543aba5f49e464b17e7e8143fc01a58c (patch) | |
| tree | 3c5b9059b07e8d0bccdf826249330bfcb8c5c1cc /src/arch/alpha/miscregfile.cc | |
| parent | 63db33c4b1cd7a071c2a2fe47bda21a73618d054 (diff) | |
| download | gem5-1c8dfd92543aba5f49e464b17e7e8143fc01a58c.tar.xz | |
inorder-alpha-port: initial inorder support of ALPHA
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions
* * *
Remove namespace from header file. Causes compiler issues that are hard to find
* * *
Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time
* * *
Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)
Diffstat (limited to 'src/arch/alpha/miscregfile.cc')
| -rw-r--r-- | src/arch/alpha/miscregfile.cc | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc index 61a86f1fb..5dc316a83 100644 --- a/src/arch/alpha/miscregfile.cc +++ b/src/arch/alpha/miscregfile.cc @@ -57,8 +57,15 @@ MiscRegFile::unserialize(Checkpoint *cp, const std::string §ion) UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs); } +MiscRegFile::MiscRegFile(BaseCPU *_cpu) +{ + cpu = _cpu; + initializeIprTable(); +} + + MiscReg -MiscRegFile::readRegNoEffect(int misc_reg) +MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid ) { switch (misc_reg) { case MISCREG_FPCR: @@ -78,7 +85,7 @@ MiscRegFile::readRegNoEffect(int misc_reg) } MiscReg -MiscRegFile::readReg(int misc_reg, ThreadContext *tc) +MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid ) { switch (misc_reg) { case MISCREG_FPCR: @@ -97,7 +104,7 @@ MiscRegFile::readReg(int misc_reg, ThreadContext *tc) } void -MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val) +MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid) { switch (misc_reg) { case MISCREG_FPCR: @@ -123,7 +130,8 @@ MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val) } void -MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc) +MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc, + unsigned tid) { switch (misc_reg) { case MISCREG_FPCR: |