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authorAli Saidi <saidi@eecs.umich.edu>2007-03-07 15:04:44 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-03-07 15:04:44 -0500
commit49527ab55312bf02dfce20c45db8f173b0c2324e (patch)
treeb9212b195a7b253940aaaab5c8b9ef27e43d026e /src/arch/alpha/miscregfile.hh
parentea7bdf9f60c404761dfc568d5291c75747a2dd88 (diff)
parent689cab36c90b56b3c8a7cda16d758acdd89f9de1 (diff)
downloadgem5-49527ab55312bf02dfce20c45db8f173b0c2324e.tar.xz
Merge zizzer:/bk/newmem
into zeep.pool:/tmp/newmem --HG-- extra : convert_revision : f078a05729b5fe464a06a58bc4adcb374f560572
Diffstat (limited to 'src/arch/alpha/miscregfile.hh')
-rw-r--r--src/arch/alpha/miscregfile.hh8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh
index 31b3e59b3..aea702849 100644
--- a/src/arch/alpha/miscregfile.hh
+++ b/src/arch/alpha/miscregfile.hh
@@ -75,18 +75,18 @@ namespace AlphaISA
#endif
}
- MiscReg readReg(int misc_reg);
+ MiscReg readRegNoEffect(int misc_reg);
- MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc);
+ MiscReg readReg(int misc_reg, ThreadContext *tc);
//These functions should be removed once the simplescalar cpu model
//has been replaced.
int getInstAsid();
int getDataAsid();
- void setReg(int misc_reg, const MiscReg &val);
+ void setRegNoEffect(int misc_reg, const MiscReg &val);
- void setRegWithEffect(int misc_reg, const MiscReg &val,
+ void setReg(int misc_reg, const MiscReg &val,
ThreadContext *tc);
void clear()