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| author | Ali Saidi <saidi@eecs.umich.edu> | 2008-09-10 14:26:15 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2008-09-10 14:26:15 -0400 |
| commit | 3a3e356f4e61e86f6f1427dd85cf1e41fa9125c0 (patch) | |
| tree | c9e147a14bcab9e4767ad13a00ac4a375044c441 /src/arch/alpha/miscregfile.hh | |
| parent | 09a8fb0b5263d4b41b8206ce075a3f6923907d65 (diff) | |
| download | gem5-3a3e356f4e61e86f6f1427dd85cf1e41fa9125c0.tar.xz | |
style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
Diffstat (limited to 'src/arch/alpha/miscregfile.hh')
| -rw-r--r-- | src/arch/alpha/miscregfile.hh | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh index 022b6404a..f07b998e6 100644 --- a/src/arch/alpha/miscregfile.hh +++ b/src/arch/alpha/miscregfile.hh @@ -60,11 +60,11 @@ namespace AlphaISA class MiscRegFile { protected: - uint64_t fpcr; // floating point condition codes - uint64_t uniq; // process-unique register - bool lock_flag; // lock flag for LL/SC - Addr lock_addr; // lock address for LL/SC - int intr_flag; + uint64_t fpcr; // floating point condition codes + uint64_t uniq; // process-unique register + bool lock_flag; // lock flag for LL/SC + Addr lock_addr; // lock address for LL/SC + int intr_flag; public: MiscRegFile() |