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author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:13 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:13 -0400 |
commit | 1c8dfd92543aba5f49e464b17e7e8143fc01a58c (patch) | |
tree | 3c5b9059b07e8d0bccdf826249330bfcb8c5c1cc /src/arch/alpha/miscregfile.hh | |
parent | 63db33c4b1cd7a071c2a2fe47bda21a73618d054 (diff) | |
download | gem5-1c8dfd92543aba5f49e464b17e7e8143fc01a58c.tar.xz |
inorder-alpha-port: initial inorder support of ALPHA
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions
* * *
Remove namespace from header file. Causes compiler issues that are hard to find
* * *
Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time
* * *
Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)
Diffstat (limited to 'src/arch/alpha/miscregfile.hh')
-rw-r--r-- | src/arch/alpha/miscregfile.hh | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh index 6105ce683..b194e00bb 100644 --- a/src/arch/alpha/miscregfile.hh +++ b/src/arch/alpha/miscregfile.hh @@ -41,6 +41,7 @@ class Checkpoint; class ThreadContext; +class BaseCPU; namespace AlphaISA { @@ -68,6 +69,8 @@ class MiscRegFile InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs + BaseCPU *cpu; + protected: InternalProcReg readIpr(int idx, ThreadContext *tc); void setIpr(int idx, InternalProcReg val, ThreadContext *tc); @@ -78,16 +81,18 @@ class MiscRegFile initializeIprTable(); } + MiscRegFile(BaseCPU *cpu); + // These functions should be removed once the simplescalar cpu // model has been replaced. int getInstAsid(); int getDataAsid(); - MiscReg readRegNoEffect(int misc_reg); - MiscReg readReg(int misc_reg, ThreadContext *tc); + MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0); + MiscReg readReg(int misc_reg, ThreadContext *tc, unsigned tid = 0); - void setRegNoEffect(int misc_reg, const MiscReg &val); - void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc); + void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0); + void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc, unsigned tid = 0); void clear() @@ -101,6 +106,16 @@ class MiscRegFile void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); + + void reset(std::string core_name, unsigned num_threads, + unsigned num_vpes, BaseCPU *_cpu) + { } + + + void expandForMultithreading(unsigned num_threads, unsigned num_vpes) + { } + + }; void copyIprs(ThreadContext *src, ThreadContext *dest); |