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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-21 12:03:22 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-21 12:03:22 -0700 |
| commit | eff122797b5bc735c6d7c797be691c0fa02032e3 (patch) | |
| tree | 1dd1cef3b2b4e044fece9a406cd0ce97d09a2da7 /src/arch/alpha/predecoder.hh | |
| parent | 83af0fdcf57175adf8077c51e9ba872dd2c04b76 (diff) | |
| parent | 5195500cdf7dc99b5367f91387eef4e9f5b65bfe (diff) | |
| download | gem5-eff122797b5bc735c6d7c797be691c0fa02032e3.tar.xz | |
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2
--HG--
extra : convert_revision : 9002940097a166c8442ae1adf41b974227968920
Diffstat (limited to 'src/arch/alpha/predecoder.hh')
| -rw-r--r-- | src/arch/alpha/predecoder.hh | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh index 0407ce99b..4887de856 100644 --- a/src/arch/alpha/predecoder.hh +++ b/src/arch/alpha/predecoder.hh @@ -44,8 +44,6 @@ namespace AlphaISA { protected: ThreadContext * tc; - //The pc of the current instruction - Addr fetchPC; //The extended machine instruction being generated ExtMachInst ext_inst; @@ -69,10 +67,8 @@ namespace AlphaISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr pc, Addr _fetchPC, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr fetchPC, MachInst inst) { - fetchPC = _fetchPC; - assert(off == 0); ext_inst = inst; #if FULL_SYSTEM if (pc && 0x1) |