diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
| commit | 537239b278f7b8171d2eb09ef7f99c332266c48f (patch) | |
| tree | 31984b63cc542f0a57ca96262477575ab0130c09 /src/arch/alpha/process.cc | |
| parent | f738afb865cd82487d6300259d6e87fb50660d2a (diff) | |
| download | gem5-537239b278f7b8171d2eb09ef7f99c332266c48f.tar.xz | |
Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
Diffstat (limited to 'src/arch/alpha/process.cc')
| -rw-r--r-- | src/arch/alpha/process.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc index 85619e493..a9848ebb5 100644 --- a/src/arch/alpha/process.cc +++ b/src/arch/alpha/process.cc @@ -71,6 +71,12 @@ AlphaLiveProcess::startup() argsInit(MachineBytes, VMPageSize); threadContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer()); + //Opperate in user mode + threadContexts[0]->setMiscRegNoEffect(IPR_ICM, 0x18); + //No super page mapping + threadContexts[0]->setMiscRegNoEffect(IPR_MCSR, 0); + //Set this to 0 for now, but it should be unique for each process + threadContexts[0]->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57); } |