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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-10-10 20:37:39 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-10-10 20:37:39 -0700 |
| commit | b4a76f0b0b2d0910bb1c1f3781717ec6747014b1 (patch) | |
| tree | 8073ef1a8ccf834a7d42ea41fd4979893c4fdefe /src/arch/alpha/process.cc | |
| parent | 9268f895d522a10f176099218df35bfe9111b7a9 (diff) | |
| download | gem5-b4a76f0b0b2d0910bb1c1f3781717ec6747014b1.tar.xz | |
Alpha: Initialize the data TLB mode IPR.
Diffstat (limited to 'src/arch/alpha/process.cc')
| -rw-r--r-- | src/arch/alpha/process.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc index c65cf2d37..f68a53a6f 100644 --- a/src/arch/alpha/process.cc +++ b/src/arch/alpha/process.cc @@ -205,7 +205,8 @@ AlphaLiveProcess::initState() ThreadContext *tc = system->getThreadContext(contextIds[0]); tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); //Operate in user mode - tc->setMiscRegNoEffect(IPR_ICM, 0x18); + tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3); + tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3); //No super page mapping tc->setMiscRegNoEffect(IPR_MCSR, 0); } |